flashrom: Fast memory accesses break module #2

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opened 2016-12-10 21:22:58 +01:00 by markus · 1 comment
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There needs to be a delay of ~10 cycles between WB commands.

There needs to be a delay of ~10 cycles between WB commands.
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Fixed in commit d3b2ea88b5 (and maybe d33b027e28).

Fixed in commit d3b2ea88b5a70ab709cd144d2a2aef4d4fc75af2 (and maybe d33b027e284b6995cf346a0c07dc9a18e4a32fbc).
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Reference: fpga/mor1kx-bemicrocv#2
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