251 lines
7.6 KiB
VHDL
251 lines
7.6 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- fancy_spi_master.vhd: An SPI PHY with advanced features.
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--
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-- Copyright (C) 2017 Markus Koch <markus@notsyncing.net>
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--
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-- This Source Code Form is subject to the terms of the Mozilla Public
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-- License, v. 2.0. If a copy of the MPL was not distributed with this
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-- file, You can obtain one at http://mozilla.org/MPL/2.0/.
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity fancy_spi_master is
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generic(
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TX_WIDTH_MAX : natural := 8; -- In bits
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RX_WIDTH_MAX : natural := 8; -- In bits
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RX_IGNORE_MAX : natural := 8; -- In bits
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SPI_CPOL : std_logic; -- SPI clock polarity. '0': Idle low, '1': Idle high
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SPI_CPHA : std_logic; -- SPI clock phase. '0': Sample on first edge, '1': Sample on second edge
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CKDIV : natural := 8; -- Clock divider for SPI clock, minimum 2
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CS_INACTIVE_DELAY : natural := 1 -- In system clock cycles
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);
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port(
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-- System Signals
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clk : in std_logic; -- System clock
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rst : in std_logic; -- Asynchronous reset
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clr : in std_logic; -- Synchronous reset
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-- TX
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tx_width : in integer range 0 to TX_WIDTH_MAX; -- Width of the next word in bits, sampled when asserting tx_next and at the beginning
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tx_enable : in std_logic; -- Enable transmission, taking this low for at least one clock cycle will trigger a CS inactive sequence
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tx_data : in std_logic_vector(TX_WIDTH_MAX - 1 downto 0); -- Data to be transmitted, MSB first, aligned to the left when tx_width /= TX_WIDTH_MAX
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tx_next : out std_logic; -- Strobe to request new data or to deassert tx_enable
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-- RX
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rx_width : in integer range 0 to RX_WIDTH_MAX; -- Width of the next word in bits, sampled when asserting rx_valid and at the beginning
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rx_valid : out std_logic; -- rx_data is valid, a new word has been received.
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rx_data : out std_logic_vector(RX_WIDTH_MAX - 1 downto 0); -- Received data, MSB first, aligned to the right when rx_width /= RX_WIDTH_MAX
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rx_ignore : in integer range 0 to RX_IGNORE_MAX; -- Bits to be ignored at the beginning of the transaction
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-- SPI HW Signals
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spi_clk : out std_logic; -- SPI clock output
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spi_cs_n : out std_logic; -- SPI chip select (low active)
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spi_mosi : out std_logic; -- SPI MOSI output
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spi_miso : in std_logic -- SPI MISO input
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);
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end entity fancy_spi_master;
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architecture RTL of fancy_spi_master is
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-- CKDIV
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signal spi_clk_en : std_logic;
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signal spi_clk_en_last : std_logic;
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signal spi_clk_i : std_logic;
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signal ckdiv_cnt : integer range 0 to CKDIV;
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signal spi_clk_event : boolean;
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-- MAIN FSM
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type state_t is (IDLE, ACTIVE, STOP);
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signal state : state_t;
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signal tx_width_i : integer range 0 to TX_WIDTH_MAX;
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signal shiftreg_out : std_logic_vector(TX_WIDTH_MAX - 1 downto 0);
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signal shiftreg_in : std_logic_vector(RX_WIDTH_MAX - 1 downto 0);
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signal bit_cnt_tx : integer range 0 to CS_INACTIVE_DELAY - 1;
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signal bit_cnt_rx : integer range 0 to RX_IGNORE_MAX; -- TODO: or RX_WIDTH_MAX or CS_INACTIVE_DELAY if bigger
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signal rx_past_ignore : boolean;
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signal rx_width_i : integer range 0 to RX_WIDTH_MAX;
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signal active_cycles : boolean;
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begin
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clk_gen : process(rst, clk) is
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procedure default_state is
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begin
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null;
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end procedure default_state;
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procedure reset_state is
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begin
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default_state;
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ckdiv_cnt <= 0;
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spi_clk_i <= SPI_CPOL;
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spi_clk_en_last <= '0';
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end procedure reset_state;
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begin
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if (rst = '1') then
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reset_state;
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elsif (rising_edge(clk)) then
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default_state;
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if (clr = '1') then
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reset_state;
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else
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if (ckdiv_cnt = 0) then
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spi_clk_en_last <= spi_clk_en;
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if (spi_clk_en_last /= spi_clk_en) then
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ckdiv_cnt <= CKDIV / 4;
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else
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if (spi_clk_i /= SPI_CPOL or spi_clk_en = '1') then
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spi_clk_i <= not spi_clk_i;
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end if;
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if (spi_clk_en = '1' or spi_clk_i = SPI_CPOL) then
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ckdiv_cnt <= CKDIV / 4;
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end if;
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end if;
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else
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ckdiv_cnt <= ckdiv_cnt - 1;
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end if;
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end if;
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end if;
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end process clk_gen;
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spi_clk <= spi_clk_i;
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spi_clk_event <= true when ckdiv_cnt = 0 and (spi_clk_en_last = spi_clk_en) else false;
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fancy_spi : process(rst, clk) is
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variable tx_break : boolean;
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variable tx_word_done : boolean;
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variable rx_word_done : boolean;
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procedure default_state is
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begin
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tx_next <= '0';
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tx_word_done := false;
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rx_word_done := false;
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rx_valid <= '0';
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end procedure default_state;
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procedure reset_state is
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begin
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default_state;
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state <= IDLE;
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tx_break := true;
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bit_cnt_tx <= 0;
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shiftreg_out <= (others => '0');
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shiftreg_in <= (others => '0');
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spi_cs_n <= '1';
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rx_past_ignore <= false;
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rx_width_i <= 0;
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tx_width_i <= 0;
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bit_cnt_rx <= 0;
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active_cycles <= false;
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spi_clk_en <= '0';
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end procedure reset_state;
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procedure load_new_tx_word is
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begin
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tx_width_i <= tx_width;
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shiftreg_out <= tx_data;
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bit_cnt_tx <= 0;
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tx_next <= '1';
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end procedure load_new_tx_word;
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procedure shift_out is
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begin
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shiftreg_out <= shiftreg_out(shiftreg_out'high - 1 downto 0) & '0';
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if (bit_cnt_tx = tx_width_i - 1) then
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bit_cnt_tx <= 0;
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tx_word_done := true;
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else
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bit_cnt_tx <= bit_cnt_tx + 1;
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end if;
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end procedure shift_out;
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procedure shift_in is
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begin
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if (rx_past_ignore) then
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shiftreg_in <= shiftreg_in(shiftreg_in'high - 1 downto 0) & spi_miso;
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if (bit_cnt_rx = rx_width_i - 1) then
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bit_cnt_rx <= 0;
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rx_word_done := true;
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else
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bit_cnt_rx <= bit_cnt_rx + 1;
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end if;
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else
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if (bit_cnt_rx = rx_ignore - 1) then
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bit_cnt_rx <= 0;
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rx_past_ignore <= true;
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else
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bit_cnt_rx <= bit_cnt_rx + 1;
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end if;
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end if;
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end procedure shift_in;
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begin
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if (rst = '1') then
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reset_state;
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elsif (rising_edge(clk)) then
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default_state;
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if (clr = '1') then
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reset_state;
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else
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if (tx_enable = '0') then
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tx_break := true;
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end if;
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case state is
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when IDLE =>
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if (tx_enable = '1') then
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if (tx_break) then
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rx_width_i <= rx_width;
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end if;
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spi_clk_en <= '1';
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state <= ACTIVE;
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tx_break := false;
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load_new_tx_word;
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spi_cs_n <= '0';
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end if;
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when ACTIVE =>
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if (spi_clk_event) then
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active_cycles <= true;
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end if;
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if (active_cycles or SPI_CPHA = '0') then
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if (spi_clk_event and spi_clk_i /= SPI_CPOL) then
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shift_out;
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if (tx_word_done) then
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if (tx_break) then
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spi_clk_en <= '0';
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else
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load_new_tx_word;
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end if;
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end if;
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elsif (spi_clk_event and spi_clk_i = SPI_CPOL) then
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if (spi_clk_en = '1') then
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shift_in;
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if (rx_word_done) then
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rx_width_i <= rx_width;
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rx_valid <= '1';
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end if;
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else
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bit_cnt_tx <= 0;
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state <= STOP;
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spi_cs_n <= '1';
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end if;
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end if;
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end if;
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when STOP =>
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if (bit_cnt_tx = CS_INACTIVE_DELAY - 1) then
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state <= IDLE;
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rx_past_ignore <= false;
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tx_break := true;
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active_cycles <= false;
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bit_cnt_rx <= 0;
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else
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bit_cnt_tx <= bit_cnt_tx + 1;
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end if;
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end case;
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end if;
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end if;
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end process fancy_spi;
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spi_mosi <= shiftreg_out(shiftreg_out'high);
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rx_data <= shiftreg_in;
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end architecture RTL;
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