mor1kx-bemicrocv/ip/intercon/rtl/clock_crossing_package.vhd

24 lines
691 B
VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_package.all;
package clock_crossing_package is
component clock_crossing is
generic(
sync_depth : natural := 2;
log2fifo : natural := 4);
port(
-- Common wishbone signals
rst : in std_logic;
-- Slave control port
slave_clk : in std_logic;
slave_i : in wishbone_slave_in;
slave_o : out wishbone_slave_out;
-- Master reader port
master_clk : in std_logic;
master_i : in wishbone_master_in;
master_o : out wishbone_master_out);
end component;
end package;