49 lines
		
	
	
		
			1.4 KiB
		
	
	
	
		
			VHDL
		
	
	
	
	
	
			
		
		
	
	
			49 lines
		
	
	
		
			1.4 KiB
		
	
	
	
		
			VHDL
		
	
	
	
	
	
| library ieee;
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| use ieee.std_logic_1164.all;
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| use ieee.numeric_std.all;
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| 
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| -- Read during write has an undefined result
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| entity rwp_ram is
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|    generic(
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|       addr_width : natural := 4;
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|       data_width : natural := 32);
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|    port(
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|       -- write port
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|       w_clk  : in  std_logic;
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|       w_en   : in  std_logic;
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|       w_addr : in  std_logic_vector(addr_width-1 downto 0);
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|       w_data : in  std_logic_vector(data_width-1 downto 0);
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|       -- read port
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|       r_clk  : in  std_logic;
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|       r_en   : in  std_logic;
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|       r_addr : in  std_logic_vector(addr_width-1 downto 0);
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|       r_data : out std_logic_vector(data_width-1 downto 0));
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| end rwp_ram;
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| 
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| architecture rtl of rwp_ram is
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|    type ram_t is array(2**addr_width-1 downto 0) of std_logic_vector(data_width-1 downto 0);
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|    signal ram : ram_t := (others => (others => '0'));
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|    
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|    -- Tell synthesizer we do not care about read during write behaviour
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|    attribute ramstyle : string;
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|    attribute ramstyle of ram : signal is "no_rw_check";
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| begin
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|    write : process(w_clk)
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|    begin
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|       if rising_edge(w_clk) then
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|          if w_en = '1' then
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|             ram(to_integer(unsigned(w_addr))) <= w_data;
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|          end if;
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|       end if;
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|    end process;
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|    
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|    read : process(r_clk)
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|    begin
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|       if rising_edge(r_clk) then
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|          if r_en = '1' then
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|             r_data <= ram(to_integer(unsigned(r_addr)));
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|          end if;
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|       end if;
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|    end process;
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| end rtl;
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