mor1kx-bemicrocv/ip/intercon/rtl/rwp_ram_package.vhd

24 lines
739 B
VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package rwp_ram_package is
-- Read during write has an undefined result
component rwp_ram is
generic(
addr_width : natural := 4;
data_width : natural := 32);
port(
-- write port
w_clk : in std_logic;
w_en : in std_logic;
w_addr : in std_logic_vector(addr_width-1 downto 0);
w_data : in std_logic_vector(data_width-1 downto 0);
-- read port
r_clk : in std_logic;
r_en : in std_logic;
r_addr : in std_logic_vector(addr_width-1 downto 0);
r_data : out std_logic_vector(data_width-1 downto 0));
end component;
end rwp_ram_package;