255 lines
9.4 KiB
VHDL
255 lines
9.4 KiB
VHDL
-- An MxS Wishbone crossbar switch.
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--
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-- All masters, slaves, and the crossbar itself must share the same WB clock.
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-- All participants must support the same data bus width.
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--
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-- If a master raises STB_O with an address not mapped by the crossbar,
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-- ERR_I will be raised. If the crossbar has overlapping address ranges,
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-- the lowest numbered slave is selected. If two masters address the same
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-- slave simultaneously, the lowest numbered master is granted access.
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--
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-- The implementation of this crossbar locks a master to a slave so long as
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-- CYC_O is held high. If the master tries to address outside the slave's
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-- address range, ERR_I will be raised.
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--
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-- Note: The LOCK signal is ignored, but the crossbar switch will not reassign
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-- the current bus master until it relinquishes CYC anyways.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.wishbone_package.all;
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entity crossbar is
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generic(
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masters : integer := 2;
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slaves : integer := 1;
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async : boolean := false
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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-- Master connections (INTERCON is a slave)
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slave_i : in wishbone_v3_slave_in_vector(masters - 1 downto 0);
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slave_o : out wishbone_v3_slave_out_vector(masters - 1 downto 0);
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-- Slave connections (INTERCON is a master)
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master_i : in wishbone_v3_master_in_vector(slaves - 1 downto 0);
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master_o : out wishbone_v3_master_out_vector(slaves - 1 downto 0);
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-- Address of the slaves connected
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address : in wishbone_address_vector(slaves - 1 downto 0);
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mask : in wishbone_address_vector(slaves - 1 downto 0)
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);
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end crossbar;
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architecture rtl of crossbar is
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type matrix is array (masters - 1 downto 0, slaves downto 0) of std_logic;
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type column is array (masters - 1 downto 0) of std_logic;
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type row is array (slaves downto 0) of std_logic;
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-- synchronous signals:
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signal previous : matrix; -- Previously connected pairs 1 -
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-- (a)synchronous signals (depending on generic):
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signal granted : matrix; -- The connections to form this cycle 1 selected previous busy
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signal issue : column; -- Did last cycle issue a request
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procedure main_logic(
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signal granted : out matrix;
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signal issue : out column;
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signal slave_i : in wishbone_v3_slave_in_vector(masters - 1 downto 0);
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signal previous : in matrix) is
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variable acc, tmp : std_logic;
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variable request : matrix; -- Which slaves do the masters address log(S) -
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variable selected : matrix; -- Which master wins arbitration log(M) request
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variable sbusy : row; -- Does the slave's previous connection persist?
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variable mbusy : column; -- Does the master's previous connection persist?
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begin
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-- A slave is busy if it services an in-progress cycle
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for slave in slaves - 1 downto 0 loop
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acc := '0';
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for master in masters - 1 downto 0 loop
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acc := acc or (previous(master, slave) and slave_i(master).CYC);
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end loop;
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sbusy(slave) := acc;
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end loop;
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sbusy(slaves) := '0'; -- Special case because the 'error device' supports multiple masters
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-- A master is busy iff it services an in-progress cycle
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for master in masters - 1 downto 0 loop
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acc := '0';
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for slave in slaves downto 0 loop
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acc := acc or previous(master, slave);
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end loop;
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mbusy(master) := acc and slave_i(master).CYC;
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end loop;
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-- Decode the request address to see if master wants access
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for master in masters - 1 downto 0 loop
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acc := '0';
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for slave in slaves - 1 downto 0 loop
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if (slave_i(master).ADR and mask(slave)) = address(slave) then
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tmp := '1';
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else
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tmp := '0';
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end if;
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acc := acc or tmp;
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request(master, slave) := slave_i(master).CYC and slave_i(master).STB and tmp;
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end loop;
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-- If no slaves match request, bind to 'error device'
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request(master, slaves) := slave_i(master).CYC and slave_i(master).STB and not acc;
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end loop;
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-- Arbitrate among the requesting masters
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-- Policy: lowest numbered master first
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for slave in slaves - 1 downto 0 loop
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acc := '0';
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-- It is possible to break the chain of LUTs here using a sort of kogge-stone network
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-- This probably only makes sense if you have more than 32 masters
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for master in 0 to masters - 1 loop
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selected(master, slave) := request(master, slave) and not acc;
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acc := acc or request(master, slave);
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end loop;
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end loop;
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-- Multiple masters can be granted access to the 'error device'
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for master in masters - 1 downto 0 loop
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selected(master, slaves) := request(master, slaves);
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end loop;
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-- Determine the master granted access
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-- Policy: if cycle still in progress, preserve the previous choice
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for slave in slaves downto 0 loop
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for master in masters - 1 downto 0 loop
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if sbusy(slave) = '1' or mbusy(master) = '1' then
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granted(master, slave) <= previous(master, slave);
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else
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granted(master, slave) <= selected(master, slave);
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end if;
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end loop;
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end loop;
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-- Record strobe status for virtual error device
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for master in masters - 1 downto 0 loop
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issue(master) <= slave_i(master).CYC and slave_i(master).STB;
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end loop;
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end main_logic;
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-- Select the master pins the slave will receive
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procedure slave_logic(signal o : out wishbone_v3_master_out;
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signal slave_i : in wishbone_v3_slave_in_vector(masters - 1 downto 0);
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signal granted : in matrix;
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slave : integer) is
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variable acc : wishbone_v3_master_out;
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variable granted_address : wishbone_address;
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variable granted_bte : wishbone_burst_type;
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variable granted_cti : wishbone_cycle_type;
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variable granted_select : wishbone_byte_select;
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variable granted_data : wishbone_data;
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begin
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acc := (
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CYC => '0',
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STB => '0',
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ADR => (others => '0'),
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BTE => (others => '0'),
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CTI => (others => '0'),
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LOCK => '0',
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SEL => (others => '0'),
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WE => '0',
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DAT => (others => '0'));
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for master in masters - 1 downto 0 loop
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granted_address := (others => granted(master, slave));
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granted_bte := (others => granted(master, slave));
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granted_cti := (others => granted(master, slave));
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granted_select := (others => granted(master, slave));
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granted_data := (others => granted(master, slave));
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acc := (
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CYC => acc.CYC or (slave_i(master).CYC and granted(master, slave)),
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STB => acc.STB or (slave_i(master).STB and granted(master, slave)),
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ADR => acc.ADR or (slave_i(master).ADR and granted_address),
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BTE => acc.BTE or (slave_i(master).BTE and granted_bte),
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CTI => acc.CTI or (slave_i(master).CTI and granted_cti),
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SEL => acc.SEL or (slave_i(master).SEL and granted_select),
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WE => acc.WE or (slave_i(master).WE and granted(master, slave)),
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LOCK => acc.LOCK or (slave_i(master).LOCK and granted(master, slave)),
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DAT => acc.DAT or (slave_i(master).DAT and granted_data));
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end loop;
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-- acc.ADR := std_logic_vector(unsigned(acc.ADR) - unsigned(address(slave))); -- Address translation
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acc.ADR := acc.ADR and not mask(slave); -- Address masking
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o <= acc;
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end slave_logic;
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-- Select the slave pins the master will receive
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procedure master_logic(signal o : out wishbone_v3_slave_out;
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signal master_i : in wishbone_v3_master_in_vector(slaves - 1 downto 0);
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signal issue : in column;
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signal previous : in matrix;
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signal granted : in matrix;
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master : integer) is
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variable acc : wishbone_v3_slave_out;
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variable granted_data : wishbone_data;
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begin
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acc := (
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ACK => '0',
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ERR => issue(master) and previous(master, slaves), -- Error device connected and strobed?
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RTY => '0',
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--STALL => granted(master, slaves),
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DAT => (others => '0'));
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-- We use inverted logic on STALL so that if no slave granted => stall
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for slave in slaves - 1 downto 0 loop
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granted_data := (others => granted(master, slave));
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acc := (
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ACK => acc.ACK or (master_i(slave).ACK and granted(master, slave)),
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ERR => acc.ERR or (master_i(slave).ERR and granted(master, slave)),
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RTY => acc.RTY or (master_i(slave).RTY and granted(master, slave)),
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--STALL => acc.STALL or (not master_i(slave).STALL and granted(master, slave)),
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DAT => acc.DAT or (master_i(slave).DAT and granted_data));
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end loop;
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--acc.STALL := not acc.STALL;
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o <= acc;
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end master_logic;
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begin
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-- If async determine granted devices
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granted_matrix : if async generate
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main_logic(granted, issue, slave_i, previous);
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end generate;
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granted_driver : if not async generate
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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granted <= (others => (others => '0'));
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issue <= (others => '0');
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else
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main_logic(granted, issue, slave_i, previous);
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end if;
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end if;
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end process;
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end generate;
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-- Make the slave connections
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slave_matrix : for slave in slaves - 1 downto 0 generate
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slave_logic(master_o(slave), slave_i, granted, slave);
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end generate;
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-- Make the master connections
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master_matrix : for master in masters - 1 downto 0 generate
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master_logic(slave_o(master), master_i, issue, previous, granted, master);
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end generate;
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-- Store the current grant to the previous registers
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main : process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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previous <= (others => (others => '0'));
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else
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previous <= granted;
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end if;
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end if;
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end process main;
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end rtl;
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