208 lines
6.3 KiB
VHDL
208 lines
6.3 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- jinn.vhd: A simple Wishbone interface, controllable via UART.
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--
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-- Copyright (C) 2017 Markus Koch <markus@notsyncing.net>
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--
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-- This Source Code Form is subject to the terms of the Mozilla Public
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-- License, v. 2.0. If a copy of the MPL was not distributed with this
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-- file, You can obtain one at http://mozilla.org/MPL/2.0/.
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-- -------------------------------------------------------------------------- --
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--
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-- Instructions:
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-- Write: TX [Write-Count] [32b Addr] [32b Data] -------- [32b Addr] [32b Data] -------- ... [Write-Count] [32b Addr] [32b Data] ...
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-- RX ----------------------------------- [8b CKS] --------------------- [8b CKS] ... ----------------------------------- ...
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--
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-- Read: TX [8b 0x0] [32b Addr] ---------- [32b Addr] ...
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-- RX ------------------- [32b Data] ---------- ...
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--
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-- Stall: TX [8b 0xFF]
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-- RX ---------
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--
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-- Reset: TX [8b 0xFE]
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-- ---------
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--
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-- Log:
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-- 2015/06/24: Created file
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-- 2015/06/24: Removed logic for tx/rx buffers
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-- 2015/07/14: Added stall/reset logic
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library ip;
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use ip.wishbone_package.all;
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entity jinn is
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port(
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clk_i : in std_logic;
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rst_i : in std_logic;
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-- Wishbone
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master_i : in wishbone_v3_master_in;
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master_o : out wishbone_v3_master_out;
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-- CPU Control
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cpu_stall : out std_logic;
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cpu_reset : out std_logic;
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-- Data link
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data_i : in std_logic_vector(7 downto 0); -- Data in from UART
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data_available : in std_logic; -- UART RX strobe
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data_o : out std_logic_vector(7 downto 0); -- Data out to UART
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data_valid_o : out std_logic; -- Data out strobe
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output_busy_i : in std_logic -- Transmit busy -> stall core
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);
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end entity jinn;
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architecture RTL of jinn is
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signal write_counter : integer range 0 to 255;
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signal position : integer range 0 to 7;
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signal address : wishbone_address;
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signal data : wishbone_data;
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signal cks : unsigned(7 downto 0);
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type state_t is (COMMAND, PARSE, EXECUTE, TXSERIAL);
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signal state : state_t;
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signal txDelay : std_logic;
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begin
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jinn_p : process(clk_i, rst_i) is
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begin
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if rst_i = '1' then
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-- RESET!
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position <= 0;
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state <= COMMAND;
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write_counter <= 0;
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data_valid_o <= '0';
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address <= (others => '0');
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data <= (others => '0');
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master_o.CYC <= '0';
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master_o.STB <= '0';
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master_o.ADR <= (others => '0');
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master_o.DAT <= (others => '0');
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master_o.WE <= '0';
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txDelay <= '0';
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cks <= (others => '0');
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cpu_stall <= '0';
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cpu_reset <= '1';
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elsif rising_edge(clk_i) then
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data_valid_o <= '0';
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master_o.CYC <= '0';
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master_o.STB <= '0';
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cpu_reset <= '0';
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case state is
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when COMMAND =>
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cks <= (others => '0');
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position <= 0;
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txDelay <= '0';
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if data_available = '1' then
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if unsigned(data_i) = x"FF" then
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cpu_stall <= '1';
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elsif unsigned(data_i) = x"FE" then
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cpu_reset <= '1';
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cpu_stall <= '0';
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else
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write_counter <= to_integer(unsigned(data_i));
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state <= PARSE;
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end if;
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end if;
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when PARSE =>
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if data_available = '1' then
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cks <= cks + unsigned(data_i); -- Sum everything, address and data
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if position < 7 then
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position <= position + 1;
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end if;
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if position < 4 then -- addr word
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--address(8 * (position + 1) - 1 downto 8 * position) <= data_i;
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address <= address(23 downto 0) & data_i;
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else -- data word
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--data(8 * (position + 1 - 4) - 1 downto 8 * (position - 4)) <= data_i;
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data <= data(23 downto 0) & data_i;
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end if;
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if (position = 7) or (position = 3 and write_counter = 0) then -- only retrieve address in read mode
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position <= 0;
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state <= EXECUTE;
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-- master_o.ADR <= address;
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-- master_o.DAT <= data;
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-- master_o.CYC <= '1';
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-- master_o.STB <= '1';
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-- if write_counter = 0 then
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-- master_o.WE <= '0';
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-- else
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-- master_o.WE <= '1';
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-- end if;
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end if;
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end if;
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when EXECUTE =>
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master_o.ADR <= address;
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master_o.DAT <= data;
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master_o.CYC <= '1';
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master_o.STB <= '1';
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if write_counter = 0 then
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master_o.WE <= '0';
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else
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master_o.WE <= '1';
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end if;
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if master_i.ERR = '1' or master_i.ACK = '1' then -- END OF transmission
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master_o.CYC <= '0';
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master_o.STB <= '0';
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if write_counter = 0 then -- read
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data <= master_i.DAT;
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state <= TXSERIAL;
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position <= 0;
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else
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write_counter <= write_counter - 1;
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if master_i.ACK = '1' then
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data <= std_logic_vector(cks) & x"000000"; -- ACK!
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else
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data <= not std_logic_vector(cks) & x"FFFFFF"; -- NAK! by sending a probably woring checksum
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end if;
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position <= 3; -- Only transmit one byte (the checksum)
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state <= TXSERIAL;
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cks <= (others => '0');
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end if;
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elsif master_i.RTY = '1' then
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null;
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-- wait
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end if;
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when TXSERIAL =>
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txDelay <= not txDelay;
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if txDelay = '0' and output_busy_i = '0' then -- only every odd cycle (uart has a busy-activate delay of 1)
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--data_o <= address(8 * (position + 1) - 1 downto 8 * position);
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data_o <= data(31 downto 24);
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data <= data(23 downto 0) & x"00";
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data_valid_o <= '1';
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if position = 3 then
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position <= 0;
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if write_counter = 0 then
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state <= COMMAND; -- R/W selector (Write-Count)
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else
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state <= PARSE; -- more writes are following directly
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end if;
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else
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position <= position + 1;
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end if;
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end if;
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end case;
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--master_o.CYC <= '0'; -- DEBUG ONLY - diasble moduel
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--master_o.STB <= '0'; -- DEBUG ONYL
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end if;
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end process jinn_p;
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master_o.SEL <= "1111";
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master_o.BTE <= (others => '0');
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master_o.CTI <= (others => '0');
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master_o.LOCK <= '0';
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end architecture RTL;
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