32 lines
680 B
VHDL
32 lines
680 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity synchronizer is
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generic(COUNT : integer := 1);
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port(
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clk : in std_logic;
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rst : in std_logic;
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dIn : in std_logic_vector(COUNT - 1 downto 0);
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dOut : out std_logic_vector(COUNT - 1 downto 0)
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);
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end entity synchronizer;
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architecture RTL of synchronizer is
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signal temp : std_logic_vector(COUNT - 1 downto 0);
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begin
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synch : process(rst, clk) is
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begin
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for i in 0 to COUNT - 1 loop
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if rst = '1' then
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temp(i) <= '0';
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dOut(i) <= '0';
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elsif rising_edge(clk) then
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temp(i) <= dIn(i);
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dOut(i) <= temp(i);
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end if;
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end loop;
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end process synch;
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end architecture RTL;
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