mor1kx-bemicrocv/bench/bench_flashrom_controller.vhd

146 lines
3.7 KiB
VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library design;
use design.all;
use design.flashrom_pkg.all;
entity bench_flashrom_controller is
end entity bench_flashrom_controller;
architecture rtl of bench_flashrom_controller is
signal clk : std_logic;
signal rst : std_logic;
procedure waitclk is
begin
wait until rising_edge(clk);
end procedure waitclk;
procedure waitnclk(n : integer) is
begin
for i in 1 to n loop
wait until rising_edge(clk);
end loop;
end procedure waitnclk;
procedure strobe(signal s : out std_logic) is
begin
s <= '1';
waitclk;
s <= '0';
waitclk;
end procedure strobe;
signal clr : std_logic;
signal ready : std_logic;
signal page : std_logic_vector(FLASHROM_ADDR_WIDTH - 1 downto 0);
signal sync_stb : std_logic;
signal load_stb : std_logic;
signal status_update_stb : std_logic;
signal status : std_logic_vector(7 downto 0);
signal info : std_logic_vector(31 downto 0);
signal data_in : std_logic_vector(7 downto 0);
signal data_in_valid : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_out_valid : std_logic;
signal spi_si : std_logic;
signal spi_so : std_logic;
signal spi_sck : std_logic;
signal spi_reset_n : std_logic;
signal spi_cs_n : std_logic;
signal spi_wp_n : std_logic;
signal spi_busy : std_logic;
signal spi_clk_cnt : integer := 0;
begin
DataFlash_inst : entity work.DataFlash
generic map(
flashmemory => "devicemodels/memory.txt",
Rapid_interface => true,
fsck => 66,
DEVICE => "AT45DB011D", --AT45DB011D
Tsck => 13.6 ns)
port map(
SI => spi_si,
CSB => spi_cs_n,
SCK => spi_sck,
WPB => spi_wp_n,
RESETB => spi_reset_n,
SO => spi_so,
RDYBSY => spi_busy
);
flashrom_controller_inst : entity design.flashrom_controller
port map(
clk => clk,
rst => rst,
clr => clr,
ready => ready,
page => page,
sync_stb => sync_stb,
load_stb => load_stb,
status_update_stb => status_update_stb,
status => status,
info => info,
data_in => data_in,
data_in_valid => data_in_valid,
data_out => data_out,
data_out_valid => data_out_valid,
spi_si => spi_si,
spi_so => spi_so,
spi_sck => spi_sck,
spi_reset_n => spi_reset_n,
spi_cs_n => spi_cs_n,
spi_wp_n => spi_wp_n
);
-- clock driver
clock_driver : process
constant PERIOD : time := 10 ns;
begin
clk <= '0';
wait for PERIOD / 2;
clk <= '1';
wait for PERIOD / 2;
end process clock_driver;
--testbench
bench : process is
begin
rst <= '1';
clr <= '0';
wait for 10 ns * 2;
wait until (rising_edge(clk));
rst <= '0';
wait for 10 ns * 2;
wait until (rising_edge(clk));
-- bench code here
wait until ready = '1';
strobe(load_stb);
wait until ready = '1';
strobe(load_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(status_update_stb);
wait until ready = '1';
strobe(load_stb);
wait;
end process bench;
spiclkcounter : process is
begin
wait until spi_sck = '1';
spi_clk_cnt <= spi_clk_cnt + 1;
end process spiclkcounter;
end architecture rtl;