93 lines
2.1 KiB
VHDL
93 lines
2.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity bench_flashrom_spi is
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end entity bench_flashrom_spi;
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library design;
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use design.all;
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architecture RTL of bench_flashrom_spi is
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signal clk : std_logic;
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signal spi_clk : std_logic;
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signal rst : std_logic;
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signal spi_si : std_logic;
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signal spi_so : std_logic;
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signal spi_sck : std_logic;
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signal spi_reset_n : std_logic;
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signal spi_cs_n : std_logic;
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signal spi_wp_n : std_logic;
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signal toSpiDataIn : STD_LOGIC_VECTOR(7 DOWNTO 0);
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signal toSpiWrite : STD_LOGIC;
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signal toSpiFull : STD_LOGIC;
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signal fromSpiDataOut : STD_LOGIC_VECTOR(7 DOWNTO 0);
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signal fromSpiRead : STD_LOGIC;
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signal fromSpiEmpty : STD_LOGIC;
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procedure waitclk is
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begin
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wait until rising_edge(clk);
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end procedure waitclk;
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procedure strobe(signal s : out std_logic) is
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begin
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s <= '1';
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waitclk;
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s <= '0';
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waitclk;
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end procedure strobe;
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begin
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flashrom_spi_inst : entity design.flashrom_spi
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port map(
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spi_clk => spi_clk,
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clk => clk,
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rst => rst,
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spi_si => spi_si,
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spi_so => spi_so,
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spi_sck => spi_sck,
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spi_reset_n => spi_reset_n,
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spi_cs_n => spi_cs_n,
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spi_wp_n => spi_wp_n,
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toSpiDataIn => toSpiDataIn,
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toSpiWrite => toSpiWrite,
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toSpiFull => toSpiFull,
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fromSpiDataOut => fromSpiDataOut,
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fromSpiRead => fromSpiRead,
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fromSpiEmpty => fromSpiEmpty
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);
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clock_driver : process
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constant period : time := 10 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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spi_clk <= clk;
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test : process is
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begin
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spi_so <= '0';
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rst <= '1';
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toSpiDataIn <= (others => '0');
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toSpiWrite <= '0';
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fromSpiRead <= '0';
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wait for 40 ns;
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rst <= '0';
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wait for 20 ns;
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toSpiDataIn <= x"55";
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strobe(toSpiWrite);
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waitclk;
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toSpiDataIn <= x"AA";
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strobe(toSpiWrite);
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wait;
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end process test;
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end architecture RTL;
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