mor1kx-bemicrocv/bench/OLDbench_flashrom_spi.vhd.old

93 lines
2.1 KiB
VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bench_flashrom_spi is
end entity bench_flashrom_spi;
library design;
use design.all;
architecture RTL of bench_flashrom_spi is
signal clk : std_logic;
signal spi_clk : std_logic;
signal rst : std_logic;
signal spi_si : std_logic;
signal spi_so : std_logic;
signal spi_sck : std_logic;
signal spi_reset_n : std_logic;
signal spi_cs_n : std_logic;
signal spi_wp_n : std_logic;
signal toSpiDataIn : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal toSpiWrite : STD_LOGIC;
signal toSpiFull : STD_LOGIC;
signal fromSpiDataOut : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal fromSpiRead : STD_LOGIC;
signal fromSpiEmpty : STD_LOGIC;
procedure waitclk is
begin
wait until rising_edge(clk);
end procedure waitclk;
procedure strobe(signal s : out std_logic) is
begin
s <= '1';
waitclk;
s <= '0';
waitclk;
end procedure strobe;
begin
flashrom_spi_inst : entity design.flashrom_spi
port map(
spi_clk => spi_clk,
clk => clk,
rst => rst,
spi_si => spi_si,
spi_so => spi_so,
spi_sck => spi_sck,
spi_reset_n => spi_reset_n,
spi_cs_n => spi_cs_n,
spi_wp_n => spi_wp_n,
toSpiDataIn => toSpiDataIn,
toSpiWrite => toSpiWrite,
toSpiFull => toSpiFull,
fromSpiDataOut => fromSpiDataOut,
fromSpiRead => fromSpiRead,
fromSpiEmpty => fromSpiEmpty
);
clock_driver : process
constant period : time := 10 ns;
begin
clk <= '0';
wait for period / 2;
clk <= '1';
wait for period / 2;
end process clock_driver;
spi_clk <= clk;
test : process is
begin
spi_so <= '0';
rst <= '1';
toSpiDataIn <= (others => '0');
toSpiWrite <= '0';
fromSpiRead <= '0';
wait for 40 ns;
rst <= '0';
wait for 20 ns;
toSpiDataIn <= x"55";
strobe(toSpiWrite);
waitclk;
toSpiDataIn <= x"AA";
strobe(toSpiWrite);
wait;
end process test;
end architecture RTL;