225 lines
7.6 KiB
Verilog
225 lines
7.6 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// This top level module chooses between the original Altera-ST JTAG Interface
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// component in ACDS version 8.1 and before, and the new one with the PLI
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// Simulation mode turned on, which adds a wrapper over the original component.
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`timescale 1 ns / 1 ns
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module altera_avalon_st_jtag_interface #(
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parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
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// for JTAG Phy, 1 for Packets to Master
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parameter UPSTREAM_FIFO_SIZE = 0,
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parameter DOWNSTREAM_FIFO_SIZE = 0,
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parameter MGMT_CHANNEL_WIDTH = -1,
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parameter EXPORT_JTAG = 0,
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parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode
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parameter PLI_PORT = 50000 // PLI Simulation Port
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) (
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input wire jtag_tck,
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input wire jtag_tms,
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input wire jtag_tdi,
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output wire jtag_tdo,
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input wire jtag_ena,
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input wire jtag_usr1,
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input wire jtag_clr,
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input wire jtag_clrn,
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input wire jtag_state_tlr,
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input wire jtag_state_rti,
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input wire jtag_state_sdrs,
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input wire jtag_state_cdr,
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input wire jtag_state_sdr,
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input wire jtag_state_e1dr,
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input wire jtag_state_pdr,
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input wire jtag_state_e2dr,
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input wire jtag_state_udr,
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input wire jtag_state_sirs,
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input wire jtag_state_cir,
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input wire jtag_state_sir,
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input wire jtag_state_e1ir,
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input wire jtag_state_pir,
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input wire jtag_state_e2ir,
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input wire jtag_state_uir,
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input wire [2:0] jtag_ir_in,
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output wire jtag_irq,
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output wire [2:0] jtag_ir_out,
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input wire clk,
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input wire reset_n,
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input wire source_ready,
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output wire [7:0] source_data,
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output wire source_valid,
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input wire [7:0] sink_data,
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input wire sink_valid,
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output wire sink_ready,
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output wire resetrequest,
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output wire debug_reset,
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output wire mgmt_valid,
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output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
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output wire mgmt_data
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);
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// Signals in the JTAG clock domain
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wire tck;
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wire tdi;
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wire tdo;
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wire [2:0] ir_in;
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wire virtual_state_cdr;
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wire virtual_state_sdr;
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wire virtual_state_udr;
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assign jtag_irq = 1'b0;
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assign jtag_ir_out = 3'b000;
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generate
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if (EXPORT_JTAG == 0) begin
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// SLD node instantiation
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altera_jtag_sld_node node (
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.tck (tck),
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.tdi (tdi),
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.tdo (tdo),
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.ir_out (1'b0),
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.ir_in (ir_in),
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.virtual_state_cdr (virtual_state_cdr),
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.virtual_state_cir (),
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.virtual_state_e1dr (),
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.virtual_state_e2dr (),
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.virtual_state_pdr (),
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.virtual_state_sdr (virtual_state_sdr),
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.virtual_state_udr (virtual_state_udr),
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.virtual_state_uir ()
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);
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assign jtag_tdo = 1'b0;
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end else begin
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assign tck = jtag_tck;
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assign tdi = jtag_tdi;
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assign jtag_tdo = tdo;
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assign ir_in = jtag_ir_in;
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assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr;
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assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr;
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assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr;
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end
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endgenerate
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generate
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if (USE_PLI == 0)
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begin : normal
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altera_jtag_dc_streaming #(
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.PURPOSE(PURPOSE),
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.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
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.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
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.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
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) jtag_dc_streaming (
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.tck (tck),
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.tdi (tdi),
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.tdo (tdo),
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.ir_in (ir_in),
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.virtual_state_cdr(virtual_state_cdr),
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.virtual_state_sdr(virtual_state_sdr),
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.virtual_state_udr(virtual_state_udr),
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.clk(clk),
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.reset_n(reset_n),
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.source_data(source_data),
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.source_valid(source_valid),
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.sink_data(sink_data),
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.sink_valid(sink_valid),
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.sink_ready(sink_ready),
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.resetrequest(resetrequest),
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.debug_reset(debug_reset),
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.mgmt_valid(mgmt_valid),
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.mgmt_channel(mgmt_channel),
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.mgmt_data(mgmt_data)
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);
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end
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else
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begin : pli_mode
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//synthesis translate_off
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reg pli_out_valid;
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reg pli_in_ready;
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reg [7 : 0] pli_out_data;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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pli_out_valid <= 0;
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pli_out_data <= 'b0;
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pli_in_ready <= 0;
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end
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else begin
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`ifdef MODEL_TECH
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$do_transaction(
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PLI_PORT,
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pli_out_valid,
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source_ready,
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pli_out_data,
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sink_valid,
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pli_in_ready,
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sink_data
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);
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`endif
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end
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end
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//synthesis translate_on
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wire [7:0] jtag_source_data;
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wire jtag_source_valid;
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wire jtag_sink_ready;
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wire jtag_resetrequest;
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altera_jtag_dc_streaming #(
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.PURPOSE(PURPOSE),
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.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
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.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
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.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
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) jtag_dc_streaming (
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.tck (tck),
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.tdi (tdi),
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.tdo (tdo),
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.ir_in (ir_in),
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.virtual_state_cdr(virtual_state_cdr),
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.virtual_state_sdr(virtual_state_sdr),
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.virtual_state_udr(virtual_state_udr),
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.clk(clk),
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.reset_n(reset_n),
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.source_data(jtag_source_data),
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.source_valid(jtag_source_valid),
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.sink_data(sink_data),
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.sink_valid(sink_valid),
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.sink_ready(jtag_sink_ready),
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.resetrequest(jtag_resetrequest)//,
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//.debug_reset(debug_reset),
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//.mgmt_valid(mgmt_valid),
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//.mgmt_channel(mgmt_channel),
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//.mgmt_data(mgmt_data)
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);
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// synthesis read_comments_as_HDL on
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// assign source_valid = jtag_source_valid;
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// assign source_data = jtag_source_data;
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// assign sink_ready = jtag_sink_ready;
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// assign resetrequest = jtag_resetrequest;
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// synthesis read_comments_as_HDL off
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//synthesis translate_off
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assign source_valid = pli_out_valid;
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assign source_data = pli_out_data;
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assign sink_ready = pli_in_ready;
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assign resetrequest = 1'b0;
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//synthesis translate_on
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assign jtag_tdo = 1'b0;
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end
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endgenerate
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endmodule
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