167 lines
5.2 KiB
Systemverilog
167 lines
5.2 KiB
Systemverilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage.sv $
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// $Revision: #1 $
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// $Date: 2015/08/09 $
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// $Author: swbranch $
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ns
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module altera_avalon_st_pipeline_stage #(
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parameter
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SYMBOLS_PER_BEAT = 1,
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BITS_PER_SYMBOL = 8,
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USE_PACKETS = 0,
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USE_EMPTY = 0,
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PIPELINE_READY = 1,
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// Optional ST signal widths. Value "0" means no such port.
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CHANNEL_WIDTH = 0,
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ERROR_WIDTH = 0,
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// Derived parameters
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DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
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PACKET_WIDTH = 0,
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EMPTY_WIDTH = 0
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)
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(
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input clk,
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input reset,
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output in_ready,
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input in_valid,
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input [DATA_WIDTH - 1 : 0] in_data,
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input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
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input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
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input in_startofpacket,
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input in_endofpacket,
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input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
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input out_ready,
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output out_valid,
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output [DATA_WIDTH - 1 : 0] out_data,
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output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
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output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
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output out_startofpacket,
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output out_endofpacket,
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output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
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);
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localparam
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PAYLOAD_WIDTH =
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DATA_WIDTH +
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PACKET_WIDTH +
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CHANNEL_WIDTH +
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EMPTY_WIDTH +
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ERROR_WIDTH;
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wire [PAYLOAD_WIDTH - 1: 0] in_payload;
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wire [PAYLOAD_WIDTH - 1: 0] out_payload;
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// Assign in_data and other optional in_* interface signals to in_payload.
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assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
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generate
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// optional packet inputs
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if (PACKET_WIDTH) begin
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assign in_payload[
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DATA_WIDTH + PACKET_WIDTH - 1 :
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DATA_WIDTH
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] = {in_startofpacket, in_endofpacket};
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end
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// optional channel input
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if (CHANNEL_WIDTH) begin
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assign in_payload[
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DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
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DATA_WIDTH + PACKET_WIDTH
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] = in_channel;
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end
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// optional empty input
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if (EMPTY_WIDTH) begin
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assign in_payload[
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DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
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DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
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] = in_empty;
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end
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// optional error input
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if (ERROR_WIDTH) begin
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assign in_payload[
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DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
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DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
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] = in_error;
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end
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endgenerate
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altera_avalon_st_pipeline_base #(
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.SYMBOLS_PER_BEAT (PAYLOAD_WIDTH),
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.BITS_PER_SYMBOL (1),
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.PIPELINE_READY (PIPELINE_READY)
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) core (
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.clk (clk),
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.reset (reset),
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.in_ready (in_ready),
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.in_valid (in_valid),
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.in_data (in_payload),
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.out_ready (out_ready),
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.out_valid (out_valid),
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.out_data (out_payload)
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);
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// Assign out_data and other optional out_* interface signals from out_payload.
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assign out_data = out_payload[DATA_WIDTH - 1 : 0];
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generate
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// optional packet outputs
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if (PACKET_WIDTH) begin
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assign {out_startofpacket, out_endofpacket} =
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out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
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end else begin
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// Avoid a "has no driver" warning.
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assign {out_startofpacket, out_endofpacket} = 2'b0;
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end
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// optional channel output
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if (CHANNEL_WIDTH) begin
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assign out_channel = out_payload[
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DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
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DATA_WIDTH + PACKET_WIDTH
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];
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end else begin
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// Avoid a "has no driver" warning.
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assign out_channel = 1'b0;
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end
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// optional empty output
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if (EMPTY_WIDTH) begin
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assign out_empty = out_payload[
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DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
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DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
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];
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end else begin
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// Avoid a "has no driver" warning.
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assign out_empty = 1'b0;
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end
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// optional error output
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if (ERROR_WIDTH) begin
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assign out_error = out_payload[
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DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
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DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
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];
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end else begin
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// Avoid a "has no driver" warning.
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assign out_error = 1'b0;
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end
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endgenerate
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endmodule
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