262 lines
6.5 KiB
Verilog
262 lines
6.5 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// synopsys translate_off
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`timescale 1 ns / 1 ns
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// synopsys translate_on
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module altera_jtag_sld_node (
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ir_out,
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tdo,
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ir_in,
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tck,
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tdi,
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virtual_state_cdr,
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virtual_state_cir,
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virtual_state_e1dr,
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virtual_state_e2dr,
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virtual_state_pdr,
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virtual_state_sdr,
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virtual_state_udr,
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virtual_state_uir
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);
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parameter TCK_FREQ_MHZ = 20;
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localparam TCK_HALF_PERIOD_US = (1000/TCK_FREQ_MHZ)/2;
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localparam IRWIDTH = 3;
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input [IRWIDTH - 1:0] ir_out;
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input tdo;
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output reg [IRWIDTH - 1:0] ir_in;
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output tck;
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output reg tdi = 1'b0;
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output virtual_state_cdr;
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output virtual_state_cir;
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output virtual_state_e1dr;
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output virtual_state_e2dr;
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output virtual_state_pdr;
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output virtual_state_sdr;
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output virtual_state_udr;
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output virtual_state_uir;
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// PHY Simulation signals
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`ifndef ALTERA_RESERVED_QIS
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reg simulation_clock;
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reg sdrs;
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reg cdr;
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reg sdr;
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reg e1dr;
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reg udr;
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reg [7:0] bit_index;
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`endif
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// PHY Instantiation
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`ifdef ALTERA_RESERVED_QIS
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wire tdi_port;
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wire [IRWIDTH - 1:0] ir_in_port;
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always @(tdi_port)
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tdi = tdi_port;
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always @(ir_in_port)
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ir_in = ir_in_port;
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sld_virtual_jtag_basic sld_virtual_jtag_component (
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.ir_out (ir_out),
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.tdo (tdo),
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.tdi (tdi_port),
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.tck (tck),
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.ir_in (ir_in_port),
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.virtual_state_cir (virtual_state_cir),
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.virtual_state_pdr (virtual_state_pdr),
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.virtual_state_uir (virtual_state_uir),
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.virtual_state_sdr (virtual_state_sdr),
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.virtual_state_cdr (virtual_state_cdr),
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.virtual_state_udr (virtual_state_udr),
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.virtual_state_e1dr (virtual_state_e1dr),
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.virtual_state_e2dr (virtual_state_e2dr)
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// synopsys translate_off
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,
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.jtag_state_cdr (),
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.jtag_state_cir (),
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.jtag_state_e1dr (),
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.jtag_state_e1ir (),
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.jtag_state_e2dr (),
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.jtag_state_e2ir (),
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.jtag_state_pdr (),
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.jtag_state_pir (),
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.jtag_state_rti (),
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.jtag_state_sdr (),
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.jtag_state_sdrs (),
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.jtag_state_sir (),
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.jtag_state_sirs (),
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.jtag_state_tlr (),
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.jtag_state_udr (),
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.jtag_state_uir (),
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.tms ()
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// synopsys translate_on
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);
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defparam
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sld_virtual_jtag_component.sld_mfg_id = 110,
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sld_virtual_jtag_component.sld_type_id = 132,
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sld_virtual_jtag_component.sld_version = 1,
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sld_virtual_jtag_component.sld_auto_instance_index = "YES",
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sld_virtual_jtag_component.sld_instance_index = 0,
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sld_virtual_jtag_component.sld_ir_width = IRWIDTH,
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sld_virtual_jtag_component.sld_sim_action = "",
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sld_virtual_jtag_component.sld_sim_n_scan = 0,
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sld_virtual_jtag_component.sld_sim_total_length = 0;
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`endif
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// PHY Simulation
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`ifndef ALTERA_RESERVED_QIS
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localparam DATA = 0;
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localparam LOOPBACK = 1;
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localparam DEBUG = 2;
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localparam INFO = 3;
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localparam CONTROL = 4;
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localparam MGMT = 5;
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always
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//#TCK_HALF_PERIOD_US simulation_clock = $random;
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#TCK_HALF_PERIOD_US simulation_clock = ~simulation_clock;
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assign tck = simulation_clock;
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assign virtual_state_cdr = cdr;
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assign virtual_state_sdr = sdr;
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assign virtual_state_e1dr = e1dr;
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assign virtual_state_udr = udr;
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task reset_jtag_state;
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begin
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simulation_clock = 0;
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enter_data_mode;
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clear_states_async;
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end
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endtask
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task enter_data_mode;
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begin
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ir_in = DATA;
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clear_states;
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end
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endtask
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task enter_loopback_mode;
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begin
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ir_in = LOOPBACK;
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clear_states;
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end
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endtask
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task enter_debug_mode;
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begin
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ir_in = DEBUG;
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clear_states;
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end
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endtask
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task enter_info_mode;
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begin
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ir_in = INFO;
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clear_states;
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end
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endtask
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task enter_control_mode;
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begin
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ir_in = CONTROL;
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clear_states;
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end
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endtask
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task enter_mgmt_mode;
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begin
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ir_in = MGMT;
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clear_states;
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end
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endtask
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task enter_sdrs_state;
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begin
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{sdrs, cdr, sdr, e1dr, udr} = 5'b10000;
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tdi = 1'b0;
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@(posedge tck);
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end
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endtask
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task enter_cdr_state;
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begin
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{sdrs, cdr, sdr, e1dr, udr} = 5'b01000;
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tdi = 1'b0;
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@(posedge tck);
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end
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endtask
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task enter_e1dr_state;
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begin
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{sdrs, cdr, sdr, e1dr, udr} = 5'b00010;
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tdi = 1'b0;
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@(posedge tck);
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end
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endtask
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task enter_udr_state;
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begin
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{sdrs, cdr, sdr, e1dr, udr} = 5'b00001;
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tdi = 1'b0;
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@(posedge tck);
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end
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endtask
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task clear_states;
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begin
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clear_states_async;
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@(posedge tck);
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end
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endtask
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task clear_states_async;
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begin
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{cdr, sdr, e1dr, udr} = 4'b0000;
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end
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endtask
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task shift_one_bit;
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input bit_to_send;
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output reg bit_received;
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begin
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{cdr, sdr, e1dr, udr} = 4'b0100;
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tdi = bit_to_send;
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@(posedge tck);
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bit_received = tdo;
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end
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endtask
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task shift_one_byte;
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input [7:0] byte_to_send;
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output reg [7:0] byte_received;
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integer i;
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reg bit_received;
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begin
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for (i=0; i<8; i=i+1)
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begin
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bit_index = i;
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shift_one_bit(byte_to_send[i], bit_received);
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byte_received[i] = bit_received;
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end
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end
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endtask
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`endif
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endmodule
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