719 lines
32 KiB
Verilog
719 lines
32 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench (
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// inputs:
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D_iw,
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D_iw_op,
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D_iw_opx,
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D_valid,
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E_alu_result,
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E_mem_byte_en,
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E_st_data,
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E_valid,
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F_pcb,
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F_valid,
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R_ctrl_exception,
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R_ctrl_ld,
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R_ctrl_ld_non_io,
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R_dst_regnum,
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R_wr_dst_reg,
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W_bstatus_reg,
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W_cmp_result,
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W_estatus_reg,
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W_ienable_reg,
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W_ipending_reg,
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W_mem_baddr,
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W_rf_wr_data,
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W_status_reg,
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W_valid,
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W_vinst,
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W_wr_data,
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av_ld_data_aligned_unfiltered,
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clk,
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d_address,
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d_byteenable,
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d_read,
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d_write_nxt,
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i_address,
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i_read,
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i_readdata,
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i_waitrequest,
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reset_n,
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// outputs:
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av_ld_data_aligned_filtered,
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d_write,
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test_has_ended
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)
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;
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output [ 31: 0] av_ld_data_aligned_filtered;
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output d_write;
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output test_has_ended;
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input [ 31: 0] D_iw;
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input [ 5: 0] D_iw_op;
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input [ 5: 0] D_iw_opx;
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input D_valid;
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input [ 31: 0] E_alu_result;
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input [ 3: 0] E_mem_byte_en;
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input [ 31: 0] E_st_data;
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input E_valid;
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input [ 16: 0] F_pcb;
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input F_valid;
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input R_ctrl_exception;
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input R_ctrl_ld;
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input R_ctrl_ld_non_io;
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input [ 4: 0] R_dst_regnum;
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input R_wr_dst_reg;
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input W_bstatus_reg;
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input W_cmp_result;
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input W_estatus_reg;
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input [ 31: 0] W_ienable_reg;
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input [ 31: 0] W_ipending_reg;
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input [ 19: 0] W_mem_baddr;
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input [ 31: 0] W_rf_wr_data;
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input W_status_reg;
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input W_valid;
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input [ 55: 0] W_vinst;
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input [ 31: 0] W_wr_data;
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input [ 31: 0] av_ld_data_aligned_unfiltered;
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input clk;
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input [ 19: 0] d_address;
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input [ 3: 0] d_byteenable;
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input d_read;
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input d_write_nxt;
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input [ 16: 0] i_address;
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input i_read;
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input [ 31: 0] i_readdata;
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input i_waitrequest;
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input reset_n;
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wire D_op_add;
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wire D_op_addi;
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wire D_op_and;
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wire D_op_andhi;
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wire D_op_andi;
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wire D_op_beq;
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wire D_op_bge;
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wire D_op_bgeu;
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wire D_op_blt;
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wire D_op_bltu;
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wire D_op_bne;
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wire D_op_br;
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wire D_op_break;
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wire D_op_bret;
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wire D_op_call;
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wire D_op_callr;
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wire D_op_cmpeq;
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wire D_op_cmpeqi;
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wire D_op_cmpge;
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wire D_op_cmpgei;
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wire D_op_cmpgeu;
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wire D_op_cmpgeui;
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wire D_op_cmplt;
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wire D_op_cmplti;
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wire D_op_cmpltu;
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wire D_op_cmpltui;
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wire D_op_cmpne;
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wire D_op_cmpnei;
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wire D_op_crst;
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wire D_op_custom;
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wire D_op_div;
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wire D_op_divu;
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wire D_op_eret;
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wire D_op_flushd;
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wire D_op_flushda;
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wire D_op_flushi;
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wire D_op_flushp;
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wire D_op_hbreak;
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wire D_op_initd;
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wire D_op_initda;
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wire D_op_initi;
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wire D_op_intr;
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wire D_op_jmp;
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wire D_op_jmpi;
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wire D_op_ldb;
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wire D_op_ldbio;
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wire D_op_ldbu;
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wire D_op_ldbuio;
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wire D_op_ldh;
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wire D_op_ldhio;
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wire D_op_ldhu;
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wire D_op_ldhuio;
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wire D_op_ldl;
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wire D_op_ldw;
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wire D_op_ldwio;
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wire D_op_mul;
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wire D_op_muli;
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wire D_op_mulxss;
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wire D_op_mulxsu;
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wire D_op_mulxuu;
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wire D_op_nextpc;
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wire D_op_nor;
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wire D_op_opx;
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wire D_op_or;
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wire D_op_orhi;
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wire D_op_ori;
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wire D_op_rdctl;
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wire D_op_rdprs;
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wire D_op_ret;
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wire D_op_rol;
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wire D_op_roli;
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wire D_op_ror;
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wire D_op_rsv02;
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wire D_op_rsv09;
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wire D_op_rsv10;
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wire D_op_rsv17;
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wire D_op_rsv18;
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wire D_op_rsv25;
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wire D_op_rsv26;
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wire D_op_rsv33;
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wire D_op_rsv34;
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wire D_op_rsv41;
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wire D_op_rsv42;
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wire D_op_rsv49;
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wire D_op_rsv57;
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wire D_op_rsv61;
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wire D_op_rsv62;
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wire D_op_rsv63;
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wire D_op_rsvx00;
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wire D_op_rsvx10;
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wire D_op_rsvx15;
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wire D_op_rsvx17;
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wire D_op_rsvx21;
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wire D_op_rsvx25;
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wire D_op_rsvx33;
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wire D_op_rsvx34;
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wire D_op_rsvx35;
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wire D_op_rsvx42;
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wire D_op_rsvx43;
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wire D_op_rsvx44;
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wire D_op_rsvx47;
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wire D_op_rsvx50;
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wire D_op_rsvx51;
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wire D_op_rsvx55;
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wire D_op_rsvx56;
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wire D_op_rsvx60;
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wire D_op_rsvx63;
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wire D_op_sll;
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wire D_op_slli;
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wire D_op_sra;
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wire D_op_srai;
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wire D_op_srl;
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wire D_op_srli;
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wire D_op_stb;
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wire D_op_stbio;
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wire D_op_stc;
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wire D_op_sth;
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wire D_op_sthio;
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wire D_op_stw;
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wire D_op_stwio;
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wire D_op_sub;
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wire D_op_sync;
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wire D_op_trap;
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wire D_op_wrctl;
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wire D_op_wrprs;
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wire D_op_xor;
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wire D_op_xorhi;
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wire D_op_xori;
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wire [ 31: 0] av_ld_data_aligned_filtered;
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wire av_ld_data_aligned_unfiltered_0_is_x;
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wire av_ld_data_aligned_unfiltered_10_is_x;
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wire av_ld_data_aligned_unfiltered_11_is_x;
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wire av_ld_data_aligned_unfiltered_12_is_x;
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wire av_ld_data_aligned_unfiltered_13_is_x;
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wire av_ld_data_aligned_unfiltered_14_is_x;
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wire av_ld_data_aligned_unfiltered_15_is_x;
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wire av_ld_data_aligned_unfiltered_16_is_x;
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wire av_ld_data_aligned_unfiltered_17_is_x;
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wire av_ld_data_aligned_unfiltered_18_is_x;
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wire av_ld_data_aligned_unfiltered_19_is_x;
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wire av_ld_data_aligned_unfiltered_1_is_x;
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wire av_ld_data_aligned_unfiltered_20_is_x;
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wire av_ld_data_aligned_unfiltered_21_is_x;
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wire av_ld_data_aligned_unfiltered_22_is_x;
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wire av_ld_data_aligned_unfiltered_23_is_x;
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wire av_ld_data_aligned_unfiltered_24_is_x;
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wire av_ld_data_aligned_unfiltered_25_is_x;
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wire av_ld_data_aligned_unfiltered_26_is_x;
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wire av_ld_data_aligned_unfiltered_27_is_x;
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wire av_ld_data_aligned_unfiltered_28_is_x;
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wire av_ld_data_aligned_unfiltered_29_is_x;
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wire av_ld_data_aligned_unfiltered_2_is_x;
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wire av_ld_data_aligned_unfiltered_30_is_x;
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wire av_ld_data_aligned_unfiltered_31_is_x;
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wire av_ld_data_aligned_unfiltered_3_is_x;
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wire av_ld_data_aligned_unfiltered_4_is_x;
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wire av_ld_data_aligned_unfiltered_5_is_x;
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wire av_ld_data_aligned_unfiltered_6_is_x;
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wire av_ld_data_aligned_unfiltered_7_is_x;
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wire av_ld_data_aligned_unfiltered_8_is_x;
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wire av_ld_data_aligned_unfiltered_9_is_x;
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reg d_write;
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wire test_has_ended;
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assign D_op_call = D_iw_op == 0;
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assign D_op_jmpi = D_iw_op == 1;
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assign D_op_ldbu = D_iw_op == 3;
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assign D_op_addi = D_iw_op == 4;
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assign D_op_stb = D_iw_op == 5;
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assign D_op_br = D_iw_op == 6;
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assign D_op_ldb = D_iw_op == 7;
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assign D_op_cmpgei = D_iw_op == 8;
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assign D_op_ldhu = D_iw_op == 11;
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assign D_op_andi = D_iw_op == 12;
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assign D_op_sth = D_iw_op == 13;
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assign D_op_bge = D_iw_op == 14;
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assign D_op_ldh = D_iw_op == 15;
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assign D_op_cmplti = D_iw_op == 16;
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assign D_op_initda = D_iw_op == 19;
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assign D_op_ori = D_iw_op == 20;
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assign D_op_stw = D_iw_op == 21;
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assign D_op_blt = D_iw_op == 22;
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assign D_op_ldw = D_iw_op == 23;
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assign D_op_cmpnei = D_iw_op == 24;
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assign D_op_flushda = D_iw_op == 27;
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assign D_op_xori = D_iw_op == 28;
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assign D_op_stc = D_iw_op == 29;
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assign D_op_bne = D_iw_op == 30;
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assign D_op_ldl = D_iw_op == 31;
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assign D_op_cmpeqi = D_iw_op == 32;
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assign D_op_ldbuio = D_iw_op == 35;
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assign D_op_muli = D_iw_op == 36;
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assign D_op_stbio = D_iw_op == 37;
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assign D_op_beq = D_iw_op == 38;
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assign D_op_ldbio = D_iw_op == 39;
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assign D_op_cmpgeui = D_iw_op == 40;
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assign D_op_ldhuio = D_iw_op == 43;
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assign D_op_andhi = D_iw_op == 44;
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assign D_op_sthio = D_iw_op == 45;
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assign D_op_bgeu = D_iw_op == 46;
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assign D_op_ldhio = D_iw_op == 47;
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assign D_op_cmpltui = D_iw_op == 48;
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assign D_op_initd = D_iw_op == 51;
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assign D_op_orhi = D_iw_op == 52;
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assign D_op_stwio = D_iw_op == 53;
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assign D_op_bltu = D_iw_op == 54;
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assign D_op_ldwio = D_iw_op == 55;
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assign D_op_rdprs = D_iw_op == 56;
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assign D_op_flushd = D_iw_op == 59;
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assign D_op_xorhi = D_iw_op == 60;
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assign D_op_rsv02 = D_iw_op == 2;
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assign D_op_rsv09 = D_iw_op == 9;
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assign D_op_rsv10 = D_iw_op == 10;
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assign D_op_rsv17 = D_iw_op == 17;
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assign D_op_rsv18 = D_iw_op == 18;
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assign D_op_rsv25 = D_iw_op == 25;
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assign D_op_rsv26 = D_iw_op == 26;
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assign D_op_rsv33 = D_iw_op == 33;
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assign D_op_rsv34 = D_iw_op == 34;
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assign D_op_rsv41 = D_iw_op == 41;
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assign D_op_rsv42 = D_iw_op == 42;
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assign D_op_rsv49 = D_iw_op == 49;
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assign D_op_rsv57 = D_iw_op == 57;
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assign D_op_rsv61 = D_iw_op == 61;
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assign D_op_rsv62 = D_iw_op == 62;
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assign D_op_rsv63 = D_iw_op == 63;
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assign D_op_eret = D_op_opx & (D_iw_opx == 1);
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assign D_op_roli = D_op_opx & (D_iw_opx == 2);
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assign D_op_rol = D_op_opx & (D_iw_opx == 3);
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assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
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assign D_op_ret = D_op_opx & (D_iw_opx == 5);
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assign D_op_nor = D_op_opx & (D_iw_opx == 6);
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assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
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assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
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assign D_op_bret = D_op_opx & (D_iw_opx == 9);
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assign D_op_ror = D_op_opx & (D_iw_opx == 11);
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assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
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assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
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assign D_op_and = D_op_opx & (D_iw_opx == 14);
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assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
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assign D_op_slli = D_op_opx & (D_iw_opx == 18);
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assign D_op_sll = D_op_opx & (D_iw_opx == 19);
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assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
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assign D_op_or = D_op_opx & (D_iw_opx == 22);
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assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
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assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
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assign D_op_srli = D_op_opx & (D_iw_opx == 26);
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assign D_op_srl = D_op_opx & (D_iw_opx == 27);
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assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
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assign D_op_callr = D_op_opx & (D_iw_opx == 29);
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assign D_op_xor = D_op_opx & (D_iw_opx == 30);
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assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
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assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
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assign D_op_divu = D_op_opx & (D_iw_opx == 36);
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assign D_op_div = D_op_opx & (D_iw_opx == 37);
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assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
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assign D_op_mul = D_op_opx & (D_iw_opx == 39);
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assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
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assign D_op_initi = D_op_opx & (D_iw_opx == 41);
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assign D_op_trap = D_op_opx & (D_iw_opx == 45);
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assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
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assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
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assign D_op_add = D_op_opx & (D_iw_opx == 49);
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assign D_op_break = D_op_opx & (D_iw_opx == 52);
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assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
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assign D_op_sync = D_op_opx & (D_iw_opx == 54);
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assign D_op_sub = D_op_opx & (D_iw_opx == 57);
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assign D_op_srai = D_op_opx & (D_iw_opx == 58);
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assign D_op_sra = D_op_opx & (D_iw_opx == 59);
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assign D_op_intr = D_op_opx & (D_iw_opx == 61);
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assign D_op_crst = D_op_opx & (D_iw_opx == 62);
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assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
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assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
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assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
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assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
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assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
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assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
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assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
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assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
|
|
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
|
|
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
|
|
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
|
|
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
|
|
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
|
|
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
|
|
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
|
|
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
|
|
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
|
|
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
|
|
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
|
|
assign D_op_opx = D_iw_op == 58;
|
|
assign D_op_custom = D_iw_op == 50;
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
d_write <= 0;
|
|
else
|
|
d_write <= d_write_nxt;
|
|
end
|
|
|
|
|
|
assign test_has_ended = 1'b0;
|
|
|
|
//synthesis translate_off
|
|
//////////////// SIMULATION-ONLY CONTENTS
|
|
//Clearing 'X' data bits
|
|
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
|
|
|
|
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
|
|
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
|
|
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
|
|
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
|
|
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
|
|
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
|
|
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
|
|
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
|
|
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
|
|
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
|
|
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
|
|
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
|
|
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
|
|
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
|
|
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
|
|
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
|
|
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
|
|
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
|
|
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
|
|
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
|
|
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
|
|
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
|
|
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
|
|
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
|
|
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
|
|
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
|
|
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
|
|
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
|
|
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
|
|
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
|
|
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
|
|
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
|
|
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset_n)
|
|
if (^(F_valid) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/F_valid is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset_n)
|
|
if (^(D_valid) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/D_valid is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset_n)
|
|
if (^(E_valid) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/E_valid is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset_n)
|
|
if (^(W_valid) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/W_valid is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
begin
|
|
end
|
|
else if (W_valid)
|
|
if (^(R_wr_dst_reg) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/R_wr_dst_reg is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
begin
|
|
end
|
|
else if (W_valid & R_wr_dst_reg)
|
|
if (^(W_wr_data) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
begin
|
|
end
|
|
else if (W_valid & R_wr_dst_reg)
|
|
if (^(R_dst_regnum) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/R_dst_regnum is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset_n)
|
|
if (^(d_write) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/d_write is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
begin
|
|
end
|
|
else if (d_write)
|
|
if (^(d_byteenable) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/d_byteenable is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
begin
|
|
end
|
|
else if (d_write | d_read)
|
|
if (^(d_address) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/d_address is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset_n)
|
|
if (^(d_read) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/d_read is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset_n)
|
|
if (^(i_read) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/i_read is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
begin
|
|
end
|
|
else if (i_read)
|
|
if (^(i_address) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/i_address is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
begin
|
|
end
|
|
else if (i_read & ~i_waitrequest)
|
|
if (^(i_readdata) === 1'bx)
|
|
begin
|
|
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/i_readdata is 'x'\n", $time);
|
|
$stop;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
begin
|
|
end
|
|
else if (W_valid & R_ctrl_ld)
|
|
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
|
|
begin
|
|
$write("%0d ns: WARNING: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge clk or negedge reset_n)
|
|
begin
|
|
if (reset_n == 0)
|
|
begin
|
|
end
|
|
else if (W_valid & R_wr_dst_reg)
|
|
if (^(W_wr_data) === 1'bx)
|
|
begin
|
|
$write("%0d ns: WARNING: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
|
|
end
|
|
end
|
|
|
|
|
|
|
|
reg [31:0] trace_handle; // for $fopen
|
|
initial
|
|
begin
|
|
trace_handle = $fopen("altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.tr");
|
|
$fwrite(trace_handle, "version 3\nnumThreads 1\n");
|
|
end
|
|
always @(posedge clk)
|
|
begin
|
|
if ((~reset_n || (W_valid)) && ~test_has_ended)
|
|
$fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, F_pcb, 0, D_op_intr, D_op_hbreak, D_iw, ~(D_op_intr | D_op_hbreak), R_wr_dst_reg, R_dst_regnum, 0, W_rf_wr_data, W_mem_baddr, E_st_data, E_mem_byte_en, W_cmp_result, E_alu_result, W_status_reg, W_estatus_reg, W_bstatus_reg, W_ienable_reg, W_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, R_ctrl_exception, 0, 0, 0, 0);
|
|
end
|
|
|
|
|
|
|
|
//////////////// END SIMULATION-ONLY CONTENTS
|
|
|
|
//synthesis translate_on
|
|
//synthesis read_comments_as_HDL on
|
|
//
|
|
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
|
|
//
|
|
//synthesis read_comments_as_HDL off
|
|
|
|
endmodule
|
|
|