100 lines
2.9 KiB
Systemverilog
100 lines
2.9 KiB
Systemverilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module altera_mem_if_sequencer_mem_no_ifdef_params (
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clk1,
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reset1,
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clken1,
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s1_address,
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s1_be,
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s1_chipselect,
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s1_write,
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s1_writedata,
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s1_readdata
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);
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parameter AVL_ADDR_WIDTH = 0;
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parameter AVL_DATA_WIDTH = 0;
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parameter AVL_SYMBOL_WIDTH = 0;
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parameter AVL_NUM_SYMBOLS = 0;
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parameter MEM_SIZE = 0;
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parameter INIT_FILE = "";
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parameter RAM_BLOCK_TYPE = "";
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localparam NUM_WORDS = MEM_SIZE / AVL_NUM_SYMBOLS;
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input clk1;
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input reset1;
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input clken1;
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input [AVL_ADDR_WIDTH - 1:0] s1_address;
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input [AVL_NUM_SYMBOLS - 1:0] s1_be;
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input s1_chipselect;
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input s1_write;
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input [AVL_DATA_WIDTH - 1:0] s1_writedata;
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output [AVL_DATA_WIDTH - 1:0] s1_readdata;
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wire wren;
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assign wren = s1_chipselect & s1_write;
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altsyncram the_altsyncram
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(
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.address_a (s1_address),
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.byteena_a (s1_be),
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.clock0 (clk1),
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.clocken0 (clken1),
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.data_a (s1_writedata),
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.q_a (s1_readdata),
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.wren_a (wren),
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.rden_a(),
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.rden_b(),
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.clocken2(),
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.clocken3(),
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.aclr0(),
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.aclr1(),
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.addressstall_a(),
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.addressstall_b(),
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.eccstatus(),
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.address_b (),
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.byteena_b (),
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.clock1 (),
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.clocken1 (),
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.data_b (),
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.q_b (),
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.wren_b ()
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);
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defparam the_altsyncram.byte_size = AVL_SYMBOL_WIDTH;
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defparam the_altsyncram.lpm_type = "altsyncram";
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defparam the_altsyncram.maximum_depth = NUM_WORDS;
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defparam the_altsyncram.numwords_a = NUM_WORDS;
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defparam the_altsyncram.outdata_reg_a = "UNREGISTERED";
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defparam the_altsyncram.ram_block_type = RAM_BLOCK_TYPE;
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defparam the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE";
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defparam the_altsyncram.width_a = AVL_DATA_WIDTH;
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defparam the_altsyncram.width_byteena_a = AVL_NUM_SYMBOLS;
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defparam the_altsyncram.widthad_a = AVL_ADDR_WIDTH;
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defparam the_altsyncram.init_file = INIT_FILE;
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defparam the_altsyncram.operation_mode = "SINGLE_PORT";
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endmodule
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