123 lines
4.0 KiB
Systemverilog
123 lines
4.0 KiB
Systemverilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1ps/1ps
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module altera_mem_if_simple_avalon_mm_bridge (
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clk,
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reset_n,
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s0_address,
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s0_read,
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s0_readdata,
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s0_write,
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s0_writedata,
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s0_waitrequest,
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s0_waitrequest_n,
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s0_byteenable,
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s0_beginbursttransfer,
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s0_burstcount,
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s0_readdatavalid,
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m0_address,
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m0_read,
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m0_readdata,
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m0_write,
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m0_writedata,
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m0_waitrequest,
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m0_byteenable,
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m0_beginbursttransfer,
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m0_burstcount,
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m0_readdatavalid
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);
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parameter DATA_WIDTH = 32;
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parameter MASTER_DATA_WIDTH = 32;
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parameter SLAVE_DATA_WIDTH = 32;
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parameter SYMBOL_WIDTH = 8;
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parameter ADDRESS_WIDTH = 10;
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parameter BURSTCOUNT_WIDTH = 1;
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parameter MASTER_ADDRESS_WIDTH = 10;
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parameter SLAVE_ADDRESS_WIDTH = 10;
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parameter WORKAROUND_HARD_PHY_ISSUE = 0;
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localparam USE_DIFFERENT_MASTER_SLAVE_ADDR = (MASTER_ADDRESS_WIDTH != SLAVE_ADDRESS_WIDTH ? 1 : 0);
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localparam S0_ADDR_WIDTH = (USE_DIFFERENT_MASTER_SLAVE_ADDR ? SLAVE_ADDRESS_WIDTH : ADDRESS_WIDTH);
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localparam M0_ADDR_WIDTH = (USE_DIFFERENT_MASTER_SLAVE_ADDR ? MASTER_ADDRESS_WIDTH : ADDRESS_WIDTH);
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localparam USE_DIFFERENT_MASTER_SLAVE_DATA = (MASTER_DATA_WIDTH != SLAVE_DATA_WIDTH ? 1 : 0);
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localparam S0_DATA_WIDTH = (USE_DIFFERENT_MASTER_SLAVE_DATA ? SLAVE_DATA_WIDTH : DATA_WIDTH);
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localparam M0_DATA_WIDTH = (USE_DIFFERENT_MASTER_SLAVE_DATA ? MASTER_DATA_WIDTH : DATA_WIDTH);
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localparam S0_BYTEEN_WIDTH = S0_DATA_WIDTH / SYMBOL_WIDTH;
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localparam M0_BYTEEN_WIDTH = M0_DATA_WIDTH / SYMBOL_WIDTH;
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input clk;
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input reset_n;
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input [S0_ADDR_WIDTH-1:0] s0_address;
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input s0_read;
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output [S0_DATA_WIDTH-1:0] s0_readdata;
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input s0_write;
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input [S0_DATA_WIDTH-1:0] s0_writedata;
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output s0_waitrequest;
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output s0_waitrequest_n;
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input [S0_BYTEEN_WIDTH-1:0] s0_byteenable;
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output s0_readdatavalid;
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input [BURSTCOUNT_WIDTH-1:0] s0_burstcount;
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input s0_beginbursttransfer;
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output [M0_ADDR_WIDTH-1:0] m0_address;
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output m0_read;
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input [M0_DATA_WIDTH-1:0] m0_readdata;
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output m0_write;
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output [M0_DATA_WIDTH-1:0] m0_writedata;
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input m0_waitrequest;
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output [M0_BYTEEN_WIDTH-1:0] m0_byteenable;
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input m0_readdatavalid;
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output [BURSTCOUNT_WIDTH-1:0] m0_burstcount;
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output m0_beginbursttransfer;
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generate
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if (WORKAROUND_HARD_PHY_ISSUE)
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begin
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reg waitrequest_r = 0;
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reg read_r = 0;
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always @(posedge clk)
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begin
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waitrequest_r <= s0_waitrequest;
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read_r <= s0_read;
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end
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assign m0_read = read_r & s0_read;
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assign s0_waitrequest = m0_waitrequest | (s0_read & ~waitrequest_r);
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assign s0_waitrequest_n = ~s0_waitrequest;
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end
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else
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begin
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assign m0_read = s0_read;
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assign s0_waitrequest = m0_waitrequest;
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assign s0_waitrequest_n = ~s0_waitrequest;
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end
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endgenerate
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assign m0_address = (M0_ADDR_WIDTH > S0_ADDR_WIDTH) ? { { (M0_ADDR_WIDTH - S0_ADDR_WIDTH) {1'b0} }, s0_address} : s0_address;
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assign s0_readdata = m0_readdata;
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assign m0_write = s0_write;
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assign m0_writedata = s0_writedata;
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assign m0_byteenable = s0_byteenable;
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assign s0_readdatavalid = m0_readdatavalid;
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assign m0_beginbursttransfer = s0_beginbursttransfer;
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assign m0_burstcount = s0_burstcount;
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endmodule
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