717 lines
30 KiB
Tcl
717 lines
30 KiB
Tcl
# (C) 2001-2015 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and other
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# software and tools, and its AMPP partner logic functions, and any output
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# files any of the foregoing (including device programming or simulation
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# files), and any associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License Subscription
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# Agreement, Altera MegaCore Function License Agreement, or other applicable
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# license agreement, including, without limitation, that your use is for the
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# sole purpose of programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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#####################################################################
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#
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# THIS IS AN AUTO-GENERATED FILE!
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# -------------------------------
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# If you modify this files, all your changes will be lost if you
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# regenerate the core!
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#
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# FILE DESCRIPTION
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# ----------------
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# This file contains the timing constraints for the UniPHY memory
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# interface.
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# * The timing parameters used by this file are assigned
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# in the ddr3_p0_timing.tcl script.
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# * The helper routines are defined in ddr3_p0_pin_map.tcl
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#
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# NOTE
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# ----
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set script_dir [file dirname [info script]]
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source "$script_dir/ddr3_p0_parameters.tcl"
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source "$script_dir/ddr3_p0_timing.tcl"
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source "$script_dir/ddr3_p0_pin_map.tcl"
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load_package ddr_timing_model
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set synthesis_flow 0
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set sta_flow 0
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set fit_flow 0
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if { $::TimeQuestInfo(nameofexecutable) == "quartus_map" } {
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set synthesis_flow 1
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} elseif { $::TimeQuestInfo(nameofexecutable) == "quartus_sta" } {
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set sta_flow 1
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} elseif { $::TimeQuestInfo(nameofexecutable) == "quartus_fit" } {
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set fit_flow 1
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}
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####################
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# #
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# GENERAL SETTINGS #
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# #
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####################
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# This is a global setting and will apply to the whole design.
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# This setting is required for the memory interface to be
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# properly constrained.
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derive_clock_uncertainty
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# Debug switch. Change to 1 to get more run-time debug information
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set debug 0
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# All timing requirements will be represented in nanoseconds with up to 3 decimal places of precision
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set_time_format -unit ns -decimal_places 3
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# Determine if entity names are on
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set entity_names_on [ ddr3_p0_are_entity_names_on ]
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##################
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# #
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# QUERIED TIMING #
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# #
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##################
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set io_standard "DIFFERENTIAL 1.5-V SSTL CLASS I"
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# This is the peak-to-peak jitter on the whole read capture path
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set DQSpathjitter [expr [get_micro_node_delay -micro DQDQS_JITTER -parameters [list IO] -in_fitter]/1000.0]
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# This is the proportion of the DQ-DQS read capture path jitter that applies to setup
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set DQSpathjitter_setup_prop [expr [get_micro_node_delay -micro DQDQS_JITTER_DIVISION -parameters [list IO] -in_fitter]/100.0]
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# This is the peak-to-peak jitter, of which half is considered to be tJITper
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set tJITper [expr [get_micro_node_delay -micro MEM_CK_PERIOD_JITTER -parameters [list IO PHY_SHORT] -in_fitter -period $t(CK)]/2000.0 + $SSN(pullin_o)]
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##################
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# #
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# DERIVED TIMING #
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# #
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##################
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# These parameters are used to make constraints more readeable
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# Half of memory clock cycle
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set half_period [ ddr3_p0_round_3dp [ expr $t(CK) / 2.0 ] ]
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# Half of reference clock
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set ref_half_period [ ddr3_p0_round_3dp [ expr $t(refCK) / 2.0 ] ]
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# Minimum delay on data output pins
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set t(wru_output_min_delay_external) [expr $t(DH) + $board(intra_DQS_group_skew) + $ISI(DQ)/2 + $ISI(DQS)/2 - $board(DQ_DQS_skew)]
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set t(wru_output_min_delay_internal) [expr $t(WL_DCD) + $t(WL_JITTER)*(1.0-$t(WL_JITTER_DIVISION)) + $SSN(rel_pullin_o)]
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set data_output_min_delay [ ddr3_p0_round_3dp [ expr - $t(wru_output_min_delay_external) - $t(wru_output_min_delay_internal)]]
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# Maximum delay on data output pins
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set t(wru_output_max_delay_external) [expr $t(DS) + $board(intra_DQS_group_skew) + $ISI(DQ)/2 + $ISI(DQS)/2 + $board(DQ_DQS_skew)]
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set t(wru_output_max_delay_internal) [expr $t(WL_DCD) + $t(WL_JITTER)*$t(WL_JITTER_DIVISION) + $SSN(rel_pushout_o)]
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set data_output_max_delay [ ddr3_p0_round_3dp [ expr $t(wru_output_max_delay_external) + $t(wru_output_max_delay_internal)]]
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# Maximum delay on data input pins
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set t(rdu_input_max_delay_external) [expr $t(DQSQ) + $board(intra_DQS_group_skew) + $board(DQ_DQS_skew) + $ISI(READ_DQ)/2 + $ISI(READ_DQS)/2]
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set t(rdu_input_max_delay_internal) [expr $DQSpathjitter*$DQSpathjitter_setup_prop + $SSN(rel_pushout_i)]
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set data_input_max_delay [ ddr3_p0_round_3dp [ expr $t(rdu_input_max_delay_external) + $t(rdu_input_max_delay_internal) ]]
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# Minimum delay on data input pins
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set t(rdu_input_min_delay_external) [expr $board(intra_DQS_group_skew) - $board(DQ_DQS_skew) + $ISI(READ_DQ)/2 + $ISI(READ_DQS)/2]
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set t(rdu_input_min_delay_internal) [expr $t(DCD) + $DQSpathjitter*(1.0-$DQSpathjitter_setup_prop) + $SSN(rel_pullin_i)]
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set data_input_min_delay [ ddr3_p0_round_3dp [ expr - $t(rdu_input_min_delay_external) - $t(rdu_input_min_delay_internal) ]]
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# Minimum delay on address and command paths
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set ac_min_delay [ ddr3_p0_round_3dp [ expr - $t(IH) -$fpga(tPLL_JITTER) - $fpga(tPLL_PSERR) - $board(intra_addr_ctrl_skew) + $board(addresscmd_CK_skew) - $ISI(addresscmd_hold) ]]
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# Maximum delay on address and command paths
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set ac_max_delay [ ddr3_p0_round_3dp [ expr $t(IS) +$fpga(tPLL_JITTER) + $fpga(tPLL_PSERR) + $board(intra_addr_ctrl_skew) + $board(addresscmd_CK_skew) + $ISI(addresscmd_setup) ]]
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if { $debug } {
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post_message -type info "SDC: Computed Parameters:"
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post_message -type info "SDC: --------------------"
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post_message -type info "SDC: half_period: $half_period"
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post_message -type info "SDC: data_output_min_delay: $data_output_min_delay"
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post_message -type info "SDC: data_output_max_delay: $data_output_max_delay"
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post_message -type info "SDC: data_input_min_delay: $data_input_min_delay"
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post_message -type info "SDC: data_input_max_delay: $data_input_max_delay"
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post_message -type info "SDC: ac_min_delay: $ac_min_delay"
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post_message -type info "SDC: ac_max_delay: $ac_max_delay"
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post_message -type info "SDC: Using Timing Models: Micro"
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}
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# This is the main call to the netlist traversal routines
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# that will automatically find all pins and registers required
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# to apply timing constraints.
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# During the fitter, the routines will be called only once
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# and cached data will be used in all subsequent calls.
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if { ! [ info exists ddr3_p0_sdc_cache ] } {
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set ddr3_p0_sdc_cache 1
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ddr3_p0_initialize_ddr_db ddr3_p0_ddr_db
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} else {
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if { $debug } {
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post_message -type info "SDC: reusing cached DDR DB"
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}
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}
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# If multiple instances of this core are present in the
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# design they will all be constrained through the
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# following loop
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set instances [ array names ddr3_p0_ddr_db ]
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foreach { inst } $instances {
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if { [ info exists pins ] } {
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# Clean-up stale content
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unset pins
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}
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array set pins $ddr3_p0_ddr_db($inst)
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set prefix $inst
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if { $entity_names_on } {
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set prefix [ string map "| |*:" $inst ]
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set prefix "*:$prefix"
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}
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#####################################################
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# #
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# Transfer the pin names to more readable variables #
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# #
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#####################################################
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set dqs_pins $pins(dqs_pins)
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set dqsn_pins $pins(dqsn_pins)
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set q_groups [ list ]
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foreach { q_group } $pins(q_groups) {
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set q_group $q_group
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lappend q_groups $q_group
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}
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set all_dq_pins [ join [ join $q_groups ] ]
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set ck_pins $pins(ck_pins)
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set ckn_pins $pins(ckn_pins)
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set add_pins $pins(add_pins)
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set ba_pins $pins(ba_pins)
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set cmd_pins $pins(cmd_pins)
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set reset_pins $pins(reset_pins)
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set ac_pins [ concat $add_pins $ba_pins $cmd_pins ]
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set dm_pins $pins(dm_pins)
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set all_dq_dm_pins [ concat $all_dq_pins $dm_pins ]
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set pll_ref_clock $pins(pll_ref_clock)
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set pll_afi_clock $pins(pll_afi_clock)
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set pll_dq_write_clock $pins(pll_dq_write_clock)
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set pll_ck_clock $pins(pll_ck_clock)
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set pll_write_clock $pins(pll_write_clock)
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set pll_avl_clock $pins(pll_avl_clock)
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set pll_avl_phy_clock $pins(pll_avl_phy_clock)
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set pll_config_clock $pins(pll_config_clock)
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set pll_driver_core_clock $pins(pll_driver_core_clock)
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set dqs_in_clocks $pins(dqs_in_clocks)
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set dqs_out_clocks $pins(dqs_out_clocks)
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set dqsn_out_clocks $pins(dqsn_out_clocks)
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set afi_reset_reg $pins(afi_reset_reg)
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set seq_reset_reg $pins(seq_reset_reg)
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set sync_reg $pins(sync_reg)
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set read_capture_ddio $pins(read_capture_ddio)
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set fifo_wraddress_reg $pins(fifo_wraddress_reg)
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set fifo_rdaddress_reg $pins(fifo_rdaddress_reg)
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set fifo_wrdata_reg $pins(fifo_wrdata_reg)
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set fifo_rddata_reg $pins(fifo_rddata_reg)
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##################
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# #
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# QUERIED TIMING #
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# #
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##################
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# Phase Jitter on DQS paths. This parameter is queried at run time
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set fpga(tDQS_PHASE_JITTER) [ expr [ get_integer_node_delay -integer $::GLOBAL_ddr3_p0_dqs_delay_chain_length -parameters {IO MAX HIGH} -src DQS_PHASE_JITTER -in_fitter ] / 1000.0 ]
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# Phase Error on DQS paths. This parameter is queried at run time
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set fpga(tDQS_PSERR) [ expr [ get_integer_node_delay -integer $::GLOBAL_ddr3_p0_dqs_delay_chain_length -parameters {IO MAX HIGH} -src DQS_PSERR -in_fitter ] / 1000.0 ]
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# Correct input min/max delay for queried parameters
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set t(rdu_input_min_delay_external) [expr $t(rdu_input_min_delay_external) + ($t(CK)/2.0 - $t(QH_time))]
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set t(rdu_input_min_delay_internal) [expr $t(rdu_input_min_delay_internal) + $fpga(tDQS_PSERR) + $tJITper]
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set t(rdu_input_max_delay_external) [expr $t(rdu_input_max_delay_external)]
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set t(rdu_input_max_delay_internal) [expr $t(rdu_input_max_delay_internal) + $fpga(tDQS_PSERR)]
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set final_data_input_max_delay [ ddr3_p0_round_3dp [ expr $data_input_max_delay + $fpga(tDQS_PSERR) ]]
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set final_data_input_min_delay [ ddr3_p0_round_3dp [ expr $data_input_min_delay - $t(CK) / 2.0 + $t(QH_time) - $fpga(tDQS_PSERR) - $tJITper]]
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if { $debug } {
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post_message -type info "SDC: Jitter Parameters"
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post_message -type info "SDC: -----------------"
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post_message -type info "SDC: DQS Phase: $::GLOBAL_ddr3_p0_dqs_delay_chain_length"
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post_message -type info "SDC: fpga(tDQS_PHASE_JITTER): $fpga(tDQS_PHASE_JITTER)"
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post_message -type info "SDC: fpga(tDQS_PSERR): $fpga(tDQS_PSERR)"
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post_message -type info "SDC: t(QH_time): $t(QH_time)"
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post_message -type info "SDC:"
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post_message -type info "SDC: Derived Parameters:"
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post_message -type info "SDC: -----------------"
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post_message -type info "SDC: Corrected data_input_max_delay: $final_data_input_max_delay"
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post_message -type info "SDC: Corrected data_input_min_delay: $final_data_input_min_delay"
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post_message -type info "SDC: -----------------"
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}
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# ----------------------- #
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# - - #
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# --- REFERENCE CLOCK --- #
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# - - #
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# ----------------------- #
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# This is the reference clock used by the PLL to derive any other clock in the core
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if { [get_collection_size [get_clocks -nowarn $pll_ref_clock]] > 0 } { remove_clock $pll_ref_clock }
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create_clock -period $t(refCK) -waveform [ list 0 $ref_half_period ] $pll_ref_clock
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# ------------------ #
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# - - #
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# --- PLL CLOCKS --- #
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# - - #
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# ------------------ #
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# AFI clock
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set local_pll_afi_clk [ ddr3_p0_get_or_add_clock_vseries \
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-target $pll_afi_clock \
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-suffix "afi_clk" \
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-source $pll_ref_clock \
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-multiply_by $::GLOBAL_ddr3_p0_pll_mult(PLL_AFI_CLK) \
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-divide_by $::GLOBAL_ddr3_p0_pll_div(PLL_AFI_CLK) \
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-phase $::GLOBAL_ddr3_p0_pll_phase(PLL_AFI_CLK) ]
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# DQ write clock
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set local_pll_dq_write_clk [ ddr3_p0_get_or_add_clock_vseries \
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-target $pll_dq_write_clock \
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-suffix "dq_write_clk" \
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-source $pll_ref_clock \
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-multiply_by $::GLOBAL_ddr3_p0_pll_mult(PLL_WRITE_CLK) \
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-divide_by $::GLOBAL_ddr3_p0_pll_div(PLL_WRITE_CLK) \
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-phase $::GLOBAL_ddr3_p0_pll_phase(PLL_WRITE_CLK) ]
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# DQS write clock
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set local_pll_write_clk [ ddr3_p0_get_or_add_clock_vseries \
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-target $pll_write_clock \
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-suffix "write_clk" \
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-source $pll_ref_clock \
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-multiply_by $::GLOBAL_ddr3_p0_pll_mult(PLL_MEM_CLK) \
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-divide_by $::GLOBAL_ddr3_p0_pll_div(PLL_MEM_CLK) \
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-phase $::GLOBAL_ddr3_p0_pll_phase(PLL_MEM_CLK) ]
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# NIOS clock
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set local_pll_avl_clock [ ddr3_p0_get_or_add_clock_vseries \
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-target $pll_avl_clock \
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-suffix "avl_clk" \
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-source $pll_ref_clock \
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-multiply_by $::GLOBAL_ddr3_p0_pll_mult(PLL_NIOS_CLK) \
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-divide_by $::GLOBAL_ddr3_p0_pll_div(PLL_NIOS_CLK) \
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-phase $::GLOBAL_ddr3_p0_pll_phase(PLL_NIOS_CLK) ]
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set mem_factor [expr double($::GLOBAL_ddr3_p0_pll_mult(PLL_MEM_CLK)) / $::GLOBAL_ddr3_p0_pll_div(PLL_MEM_CLK)]
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set avl_factor [expr double($::GLOBAL_ddr3_p0_pll_mult(PLL_NIOS_CLK)) / $::GLOBAL_ddr3_p0_pll_div(PLL_NIOS_CLK)]
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set write_to_avl_clk_ratio [expr int($mem_factor / $avl_factor)]
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# AVL PHY clock
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if {[get_collection_size [get_registers -nowarn $pins(avl_phy_ck_pins)]] > 0} {
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set local_pll_avl_phy_clk [ ddr3_p0_get_or_add_clock_vseries \
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-target $pll_avl_phy_clock \
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-suffix "avl_phy_clk" \
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-source $pll_ref_clock \
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-multiply_by $::GLOBAL_ddr3_p0_pll_mult(PLL_NIOS_CLK) \
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-divide_by $::GLOBAL_ddr3_p0_pll_div(PLL_NIOS_CLK) \
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-phase $::GLOBAL_ddr3_p0_pll_phase(PLL_NIOS_CLK) ]
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}
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# I/O scan chain clock
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set local_pll_config_clock [ ddr3_p0_get_or_add_clock_vseries \
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-target $pll_config_clock \
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-suffix "config_clk" \
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-source $pll_ref_clock \
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-multiply_by $::GLOBAL_ddr3_p0_pll_mult(PLL_CONFIG_CLK) \
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-divide_by $::GLOBAL_ddr3_p0_pll_div(PLL_CONFIG_CLK) \
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-phase $::GLOBAL_ddr3_p0_pll_phase(PLL_CONFIG_CLK) ]
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# Pulse-generator used by DQS tracking
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set local_sampling_clock "${inst}|ddr3_p0_sampling_clock"
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if {[get_collection_size [get_registers -nowarn $pins(dqs_enable_regs_pins)]] > 0} {
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create_generated_clock \
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-add \
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-name $local_sampling_clock \
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-source $pll_write_clock \
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-multiply_by 1 \
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-divide_by 1 \
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-phase 0 \
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$pins(dqs_enable_regs_pins)
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}
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# If this is the example design, then we need to find the PLL output which is used in the core by the driver and MPFE ports.
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# The node name is known; check to see if it exists (implying the example design) before creating the clock.
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if {[string compare -nocase $pll_driver_core_clock "_UNDEFINED_PIN_"] != 0} {
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set local_pll_driver_core_clk [ ddr3_p0_get_or_add_clock_vseries \
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-target $pll_driver_core_clock \
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-suffix "driver_core_clk" \
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-source $pll_ref_clock \
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-multiply_by 1 \
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-divide_by 1 \
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-phase 0 ]
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}
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# -------------------- #
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# - - #
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# --- SYSTEM CLOCK --- #
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# - - #
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# -------------------- #
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# This is the CK clock
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foreach { ck_pin } $ck_pins {
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create_generated_clock -multiply_by 1 -source $pll_write_clock -master_clock "$local_pll_write_clk" $ck_pin -name $ck_pin
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set_clock_uncertainty -to [ get_clocks $ck_pin ] $t(WL_JITTER)
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}
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# This is the CK#clock
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foreach { ckn_pin } $ckn_pins {
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create_generated_clock -multiply_by 1 -invert -source $pll_write_clock -master_clock "$local_pll_write_clk" $ckn_pin -name $ckn_pin
|
|
set_clock_uncertainty -to [ get_clocks $ckn_pin ] $t(WL_JITTER)
|
|
}
|
|
|
|
# ------------------- #
|
|
# - - #
|
|
# --- READ CLOCKS --- #
|
|
# - - #
|
|
# ------------------- #
|
|
|
|
foreach dqs_in_clock_struct $dqs_in_clocks {
|
|
array set dqs_in_clock $dqs_in_clock_struct
|
|
# This is the DQS clock for Read Capture analysis (micro model)
|
|
create_clock -period $t(CK) -waveform [ list 0 $half_period ] $dqs_in_clock(dqs_pin) -name $dqs_in_clock(dqs_pin)_IN -add
|
|
|
|
# Clock Uncertainty is accounted for by the ...pathjitter parameters
|
|
set_clock_uncertainty -from [ get_clocks $dqs_in_clock(dqs_pin)_IN ] 0
|
|
}
|
|
|
|
# -------------------- #
|
|
# - - #
|
|
# --- WRITE CLOCKS --- #
|
|
# - - #
|
|
# -------------------- #
|
|
|
|
# This is the DQS clock for Data Write analysis (micro model)
|
|
foreach dqs_out_clock_struct $dqs_out_clocks {
|
|
array set dqs_out_clock $dqs_out_clock_struct
|
|
create_generated_clock -multiply_by 1 -master_clock [get_clocks $local_pll_write_clk] -source $pll_write_clock $dqs_out_clock(dst) -name $dqs_out_clock(dst)_OUT -add
|
|
|
|
# Clock Uncertainty is accounted for by the ...pathjitter parameters
|
|
set_clock_uncertainty -to [ get_clocks $dqs_out_clock(dst)_OUT ] 0
|
|
}
|
|
|
|
# This is the DQS#clock for Data Write analysis (micro model)
|
|
foreach dqsn_out_clock_struct $dqsn_out_clocks {
|
|
array set dqsn_out_clock $dqsn_out_clock_struct
|
|
create_generated_clock -multiply_by 1 -master_clock [get_clocks $local_pll_write_clk] -source $pll_write_clock $dqsn_out_clock(dst) -name $dqsn_out_clock(dst)_OUT -add
|
|
|
|
# Clock Uncertainty is accounted for by the ...pathjitter parameters
|
|
set_clock_uncertainty -to [ get_clocks $dqsn_out_clock(dst)_OUT ] 0
|
|
}
|
|
|
|
##################
|
|
# #
|
|
# READ DATA PATH #
|
|
# #
|
|
##################
|
|
|
|
foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups {
|
|
foreach { dq_pin } $dq_pins {
|
|
if {[get_collection_size [get_registers -nowarn $read_capture_ddio]] > 0} {
|
|
set_max_delay -from [get_ports $dq_pin] -to $read_capture_ddio 0
|
|
set_min_delay -from [get_ports $dq_pin] -to $read_capture_ddio [expr 0-$half_period]
|
|
}
|
|
|
|
# Specifies the maximum delay difference between the DQ pin and the DQS pin:
|
|
set_input_delay -max $final_data_input_max_delay -clock [get_clocks ${dqs_pin}_IN ] [get_ports $dq_pin] -add_delay
|
|
|
|
# Specifies the minimum delay difference between the DQ pin and the DQS pin:
|
|
set_input_delay -min $final_data_input_min_delay -clock [get_clocks ${dqs_pin}_IN ] [get_ports $dq_pin] -add_delay
|
|
}
|
|
}
|
|
|
|
###################
|
|
# #
|
|
# WRITE DATA PATH #
|
|
# #
|
|
###################
|
|
|
|
foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups {
|
|
foreach { dq_pin } $dq_pins {
|
|
# Specifies the minimum delay difference between the DQS pin and the DQ pins:
|
|
set_output_delay -min $data_output_min_delay -clock [get_clocks ${dqs_pin}_OUT ] [get_ports $dq_pin] -add_delay
|
|
|
|
# Specifies the maximum delay difference between the DQS pin and the DQ pins:
|
|
set_output_delay -max $data_output_max_delay -clock [get_clocks ${dqs_pin}_OUT ] [get_ports $dq_pin] -add_delay
|
|
}
|
|
}
|
|
|
|
foreach { dqsn_pin } $dqsn_pins { dq_pins } $q_groups {
|
|
foreach { dq_pin } $dq_pins {
|
|
# Specifies the minimum delay difference between the DQS#pin and the DQ pins:
|
|
set_output_delay -min $data_output_min_delay -clock [get_clocks ${dqsn_pin}_OUT ] [get_ports $dq_pin] -add_delay
|
|
|
|
# Specifies the maximum delay difference between the DQS#pin and the DQ pins:
|
|
set_output_delay -max $data_output_max_delay -clock [get_clocks ${dqsn_pin}_OUT ] [get_ports $dq_pin] -add_delay
|
|
}
|
|
}
|
|
|
|
foreach dqs_out_clock_struct $dqs_out_clocks {
|
|
array set dqs_out_clock $dqs_out_clock_struct
|
|
|
|
if { [string length $dqs_out_clock(dm_pin)] > 0 } {
|
|
# Specifies the minimum delay difference between the DQS and the DM pins:
|
|
set_output_delay -min $data_output_min_delay -clock [get_clocks $dqs_out_clock(dst)_OUT ] [get_ports $dqs_out_clock(dm_pin)] -add_delay
|
|
|
|
# Specifies the maximum delay difference between the DQS and the DM pins:
|
|
set_output_delay -max $data_output_max_delay -clock [get_clocks $dqs_out_clock(dst)_OUT ] [get_ports $dqs_out_clock(dm_pin)] -add_delay
|
|
}
|
|
}
|
|
|
|
foreach dqsn_out_clock_struct $dqsn_out_clocks {
|
|
array set dqsn_out_clock $dqsn_out_clock_struct
|
|
|
|
if { [string length $dqsn_out_clock(dm_pin)] > 0 } {
|
|
# Specifies the minimum delay difference between the DQS and the DM pins:
|
|
set_output_delay -min $data_output_min_delay -clock [get_clocks $dqsn_out_clock(dst)_OUT ] [get_ports $dqsn_out_clock(dm_pin)] -add_delay
|
|
|
|
# Specifies the maximum delay difference between the DQS and the DM pins:
|
|
set_output_delay -max $data_output_max_delay -clock [get_clocks $dqsn_out_clock(dst)_OUT ] [get_ports $dqsn_out_clock(dm_pin)] -add_delay
|
|
}
|
|
}
|
|
|
|
##################
|
|
# #
|
|
# DQS vs CK PATH #
|
|
# #
|
|
##################
|
|
|
|
foreach { ck_pin } $ck_pins {
|
|
set_output_delay -add_delay -clock [get_clocks $ck_pin] -max [ddr3_p0_round_3dp [expr $t(CK) - $t(DQSS)*$t(CK) - $board(minCK_DQS_skew) ]] $dqs_pins
|
|
set_output_delay -add_delay -clock [get_clocks $ck_pin] -min [ddr3_p0_round_3dp [expr $t(DQSS)*$t(CK) - $board(maxCK_DQS_skew) ]] $dqs_pins
|
|
set_false_path -to [get_clocks $ck_pin] -fall_from [get_clocks $local_pll_write_clk ]
|
|
}
|
|
|
|
############
|
|
# #
|
|
# A/C PATH #
|
|
# #
|
|
############
|
|
|
|
foreach { ck_pin } $ck_pins {
|
|
# ac_pins can contain input ports such as mem_err_out_n
|
|
# Loop through each ac pin to make sure we only apply set_output_delay to output ports
|
|
foreach { ac_pin } $ac_pins {
|
|
set ac_port [ get_ports $ac_pin ]
|
|
if {[get_collection_size $ac_port] > 0} {
|
|
if [ get_port_info -is_output_port $ac_port ] {
|
|
# Specifies the minimum delay difference between the DQS pin and the address/control pins:
|
|
set_output_delay -min [ddr3_p0_round_3dp [expr {$ac_min_delay + $t(CK)/2}]] -clock [get_clocks $ck_pin] $ac_port -add_delay
|
|
|
|
# Specifies the maximum delay difference between the DQS pin and the address/control pins:
|
|
set_output_delay -max [ddr3_p0_round_3dp [expr {$ac_max_delay + $t(CK)/2}]] -clock [get_clocks $ck_pin] $ac_port -add_delay
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
# Only the rising edge-launched control data needs to be timing analyzed in full rate
|
|
set_false_path -fall_from [ get_clocks ${local_pll_write_clk} ] -to [ get_ports $ac_pins ]
|
|
|
|
##########################
|
|
# #
|
|
# MULTICYCLE CONSTRAINTS #
|
|
# #
|
|
##########################
|
|
|
|
|
|
# If powerdown feature is enabled, multicycle path from core logic to the CK generator.
|
|
# The PHY must be idle several cycles before entering and after exiting powerdown mode.
|
|
if { [get_collection_size [get_registers -nowarn ${prefix}|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*clock_gen[*].umem_ck_pad|*]] > 0 } {
|
|
set_multicycle_path -to [get_registers ${prefix}|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*clock_gen[*].umem_ck_pad|*] -end -setup 4
|
|
set_multicycle_path -to [get_registers ${prefix}|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*clock_gen[*].umem_ck_pad|*] -end -hold 4
|
|
}
|
|
|
|
|
|
|
|
# These transfers are from a full-rate clock to a "half-rate" clock (this may be even slower than half-rate).
|
|
# The transfer should be allowed up to the entire slow (latch) period, but the STA analysis
|
|
# is interpreted as one fast period. We can at least force it to use 2 fast periods.
|
|
set_multicycle_path -from [get_clocks $local_pll_write_clk] -to [get_clocks $local_pll_avl_clock] -start -setup $write_to_avl_clk_ratio
|
|
set_multicycle_path -from [get_clocks $local_pll_write_clk] -to [get_clocks $local_pll_avl_clock] -start -hold [expr $write_to_avl_clk_ratio - 1]
|
|
|
|
|
|
|
|
set read_fifo_read_dff ${prefix}|*p0|*altdq_dqs2_inst|*read_fifo~OUTPUT_DFF_*
|
|
set read_fifo_write_address_dff ${prefix}|*p0|*altdq_dqs2_inst|*read_fifo~WRITE_ADDRESS_DFF
|
|
set read_fifo_read_address_dff ${prefix}|*p0|*altdq_dqs2_inst|*read_fifo~READ_ADDRESS_DFF
|
|
set lfifo_in_read_en_dff ${prefix}|*p0|*lfifo~LFIFO_IN_READ_EN_DFF
|
|
set lfifo_in_read_en_full_dff ${prefix}|*p0|*lfifo~LFIFO_IN_READ_EN_FULL_DFF
|
|
set lfifo_dff_reg ${prefix}|*p0|*lfifo~LFIFO_OUT_OCT_LFIFO_DFF
|
|
set lfifo_out_rden_dff ${prefix}|*p0|*lfifo~LFIFO_OUT_RDEN_DFF
|
|
set lfifo_out_rdata_valid_dff ${prefix}|*p0|*lfifo~LFIFO_OUT_RDATA_VALID_DFF
|
|
set os_oct_ddio_oe_reg ${prefix}|*p0|*os_oct_ddio_oe~DFF
|
|
set lfifo_rd_latency_dff ${prefix}|*p0|*lfifo~RD_LATENCY_DFF*
|
|
set vfifo_qvld_in_dff ${prefix}|*p0|*altdq_dqs2_inst|vfifo~QVLD_IN_DFF
|
|
set vfifo_inc_wr_ptr_dff ${prefix}|*p0|*vfifo~INC_WR_PTR_DFF
|
|
set phase_align_dff ${prefix}|*p0|*altdq_dqs2_inst|phase_align_os~DFF*
|
|
set os_oe_reg ${prefix}|*p0|*os_oe_reg
|
|
set phase_align_dff ${prefix}|*p0|*phase_align_os~DFF*
|
|
set hphy_ff ${prefix}|*p0|*umemphy|hphy_inst~FF_*
|
|
set hmc_ff ${prefix}|*c0|hmc_inst~FF_*
|
|
set phy_read_latency_counter $hphy_ff
|
|
set read_fifo_reset $hphy_ff
|
|
set phy_reset_mem_stable $hphy_ff
|
|
|
|
set after_u2b 0
|
|
if {[get_collection_size [get_registers -nowarn $read_fifo_write_address_dff]] > 0} {
|
|
set after_u2b 1
|
|
}
|
|
|
|
if {$after_u2b} {
|
|
|
|
set_multicycle_path -from $hphy_ff -to $lfifo_in_read_en_full_dff -end -setup 2
|
|
set_multicycle_path -from $hphy_ff -to $lfifo_in_read_en_full_dff -end -hold 1
|
|
|
|
set_multicycle_path -from $read_fifo_reset -to $read_fifo_read_address_dff -end -setup 2
|
|
set_multicycle_path -from $read_fifo_reset -to $read_fifo_read_address_dff -end -hold 1
|
|
|
|
if {$::GLOBAL_ddr3_p0_pll_phase(PLL_NIOS_CLK) > 0} {
|
|
if {[get_collection_size [get_registers -nowarn $pins(avl_phy_ck_pins)]] > 0} {
|
|
set_multicycle_path -from [get_clocks $local_pll_afi_clk] -to [get_clocks $local_pll_avl_phy_clk] -setup 2
|
|
set_multicycle_path -from [get_clocks $local_pll_afi_clk] -to [get_clocks $local_pll_avl_phy_clk] -hold 1
|
|
|
|
set_multicycle_path -from [get_clocks $local_pll_write_clk] -to [get_clocks $local_pll_avl_phy_clk] -setup 2
|
|
set_multicycle_path -from [get_clocks $local_pll_write_clk] -to [get_clocks $local_pll_avl_phy_clk] -hold 1
|
|
}
|
|
|
|
set_multicycle_path -from [get_clocks $local_pll_config_clock] -to [get_clocks $local_pll_avl_clock] -setup 2
|
|
set_multicycle_path -from [get_clocks $local_pll_config_clock] -to [get_clocks $local_pll_avl_clock] -hold 1
|
|
}
|
|
|
|
set_false_path -from $hmc_ff -to ${prefix}|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*ddio_out*
|
|
set_false_path -from $hphy_ff -to $lfifo_in_read_en_dff
|
|
set_false_path -from $hmc_ff -to $lfifo_in_read_en_dff
|
|
set_false_path -from $hphy_ff -to $vfifo_inc_wr_ptr_dff
|
|
set_false_path -from $hmc_ff -to $vfifo_qvld_in_dff
|
|
set_false_path -from $lfifo_out_rdata_valid_dff -to $hphy_ff
|
|
set_false_path -from $phy_reset_mem_stable -to $vfifo_qvld_in_dff
|
|
set_false_path -from $phy_read_latency_counter -to $lfifo_rd_latency_dff
|
|
set_false_path -from $hphy_ff -to ${prefix}|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*ddio_out*
|
|
set_false_path -from $hphy_ff -to ${prefix}|*p0|*umemphy|*altdq_dqs2_inst|*output_path_gen[*].ddio_out*
|
|
set_false_path -from $hphy_ff -to ${prefix}|*p0|*umemphy|*altdq_dqs2_inst|extra_output_pad_gen[*].ddio_out*
|
|
set_false_path -from $hphy_ff -to $hphy_ff
|
|
set_false_path -from $hmc_ff -to $hphy_ff
|
|
set_false_path -from $hphy_ff -to $hmc_ff
|
|
set_false_path -from $hphy_ff -to $phase_align_dff
|
|
set_false_path -from ${prefix}|*s0|* -to [get_clocks $local_pll_write_clk]
|
|
set_false_path -from [get_clocks $local_pll_write_clk] -to ${prefix}|*s0|*hphy_bridge_s0_translator|av_readdata_pre[*]
|
|
|
|
set_false_path -from [get_clocks $local_pll_avl_phy_clk] -to [get_clocks $local_pll_write_clk]
|
|
|
|
}
|
|
|
|
|
|
if { [get_collection_size [get_registers -nowarn ${prefix}|*p0|*umemphy|*phy_csr_inst|*csr_register_0004[*]]] > 0 } {
|
|
set_multicycle_path -to [get_registers ${prefix}|*p0|*umemphy|*phy_csr_inst|*csr_register_0004[*]] -end -setup 2
|
|
set_multicycle_path -to [get_registers ${prefix}|*p0|*umemphy|*phy_csr_inst|*csr_register_0004[*]] -end -hold 1
|
|
}
|
|
|
|
##########################
|
|
# #
|
|
# FALSE PATH CONSTRAINTS #
|
|
# #
|
|
##########################
|
|
|
|
# Cut paths for memory clocks / async resets to avoid unconstrained warnings
|
|
foreach { pin } [concat $dqsn_pins $ck_pins $ckn_pins $reset_pins] {
|
|
set_false_path -to [get_ports $pin]
|
|
}
|
|
|
|
if { ! $synthesis_flow } {
|
|
foreach dqs_in_clock_struct $dqs_in_clocks dqsn_out_clock_struct $dqsn_out_clocks {
|
|
array set dqs_in_clock $dqs_in_clock_struct
|
|
array set dqsn_out_clock $dqsn_out_clock_struct
|
|
|
|
set_clock_groups -physically_exclusive -group "$dqs_in_clock(dqs_pin)_IN" -group "$dqs_in_clock(dqs_pin)_OUT $dqsn_out_clock(dst)_OUT"
|
|
|
|
# Cut paths between AFI Clock and Read Capture Registers
|
|
set_false_path -from [get_clocks $local_pll_afi_clk] -to [get_clocks $dqs_in_clock(dqs_pin)_IN]
|
|
|
|
}
|
|
}
|
|
|
|
foreach dqs_out_clock_struct $dqs_out_clocks {
|
|
array set dqs_out_clock $dqs_out_clock_struct
|
|
set_false_path -from $read_fifo_reset -to [ get_clocks $dqs_out_clock(dst)_OUT ]
|
|
}
|
|
|
|
# The paths between DQS_ENA_CLK and DQS_IN are calibrated, so they must not be analyzed
|
|
set_false_path -from [get_clocks $local_pll_write_clk] -to [get_clocks {*_IN}]
|
|
|
|
|
|
|
|
# The following registers serve as anchors for the pin_map.tcl
|
|
# script and are not used by the IP during memory operation
|
|
|
|
# Cut internal calibrated paths
|
|
set dqs_delay_chain_pst_dff ${prefix}|*p0|*altdq_dqs2_inst|dqs_delay_chain~POSTAMBLE_DFF
|
|
if {$after_u2b} {
|
|
set_false_path -from ${prefix}|*p0|*altdq_dqs2_inst|dqs_enable_ctrl~* -to $dqs_delay_chain_pst_dff
|
|
}
|
|
|
|
|
|
# ------------------------------ #
|
|
# - - #
|
|
# --- FITTER OVERCONSTRAINTS --- #
|
|
# - - #
|
|
# ------------------------------ #
|
|
if {$fit_flow} {
|
|
|
|
|
|
if {[get_collection_size [get_registers -nowarn $pins(avl_phy_ck_pins)]] > 0} {
|
|
set_clock_uncertainty -from [get_clocks $local_pll_afi_clk] -to [get_clocks $local_pll_avl_phy_clk] -add -setup 0.300
|
|
}
|
|
if {[get_collection_size [get_registers -nowarn $pins(avl_phy_ck_pins)]] > 0} {
|
|
set_clock_uncertainty -from [get_clocks $local_pll_avl_phy_clk] -to [get_clocks $local_pll_avl_clock] -add -hold 0.150
|
|
set_clock_uncertainty -from [get_clocks $local_pll_avl_clock] -to [get_clocks $local_pll_avl_phy_clk] -add -hold 0.150
|
|
}
|
|
set_min_delay -to $hmc_ff 0.500
|
|
|
|
}
|
|
|
|
# -------------------------------- #
|
|
# - - #
|
|
# --- TIMING MODEL ADJUSTMENTS --- #
|
|
# - - #
|
|
# -------------------------------- #
|
|
|
|
}
|
|
|
|
if {(($::quartus(nameofexecutable) ne "quartus_fit") && ($::quartus(nameofexecutable) ne "quartus_map"))} {
|
|
set dqs_clocks [ddr3_p0_get_all_instances_dqs_pins ddr3_p0_ddr_db]
|
|
# Leave clocks active when in debug mode
|
|
if {[llength $dqs_clocks] > 0 && !$debug} {
|
|
post_sdc_message info "Setting DQS clocks as inactive; use Report DDR to timing analyze DQS clocks"
|
|
set_active_clocks [remove_from_collection [get_active_clocks] [get_clocks $dqs_clocks]]
|
|
}
|
|
}
|
|
|
|
######################
|
|
# #
|
|
# REPORT DDR COMMAND #
|
|
# #
|
|
######################
|
|
|
|
add_ddr_report_command "source [list [file join [file dirname [info script]] ${::GLOBAL_ddr3_p0_corename}_report_timing.tcl]]"
|
|
|