425 lines
17 KiB
Tcl
425 lines
17 KiB
Tcl
# (C) 2001-2015 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and other
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# software and tools, and its AMPP partner logic functions, and any output
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# files any of the foregoing (including device programming or simulation
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# files), and any associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License Subscription
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# Agreement, Altera MegaCore Function License Agreement, or other applicable
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# license agreement, including, without limitation, that your use is for the
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# sole purpose of programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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#####################################################################
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#
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# THIS IS AN AUTO-GENERATED FILE!
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# -------------------------------
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# If you modify this files, all your changes will be lost if you
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# regenerate the core!
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#
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# FILE DESCRIPTION
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# ----------------
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# This file contains a simple script to automatically apply
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# IO standards and other IO assignments for the UniPHY memory
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# interface pins that connect to the memory device. The pins
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# are automatically detected using the routines defined in
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# the ddr3_p0_pin_map.tcl script.
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# All the memory interface parameters are defined in the
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# ddr3_p0_parameters.tcl script
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set available_options {
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{ c.arg "#_ignore_#" "Option to specify the revision name" }
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}
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package require cmdline
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set script_dir [file dirname [info script]]
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global ::GLOBAL_ddr3_p0_corename
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global ::GLOBAL_ddr3_p0_io_standard
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global ::GLOBAL_ddr3_p0_io_standard_differential
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global ::GLOBAL_ddr3_p0_dqs_group_size
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global ::GLOBAL_ddr3_p0_number_of_dqs_groups
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global ::GLOBAL_ddr3_p0_uniphy_temp_ver_code
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#################
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# #
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# SETUP SECTION #
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# #
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#################
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global options
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set argument_list $quartus(args)
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set argv0 "quartus_sta -t [info script]"
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set usage "\[<options>\] <project_name>:"
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if [catch {array set options [cmdline::getoptions argument_list $::available_options]} result] {
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if {[llength $argument_list] > 0 } {
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post_message -type error "Illegal Options"
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post_message -type error [::cmdline::usage $::available_options $usage]
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qexit -error
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} else {
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post_message -type info "Usage:"
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post_message -type info [::cmdline::usage $::available_options $usage]
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qexit -success
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}
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}
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if {$options(c) != "#_ignore_#"} {
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if [string compare [file extension $options(c)] ""] {
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set options(c) [file rootname $options(c)]
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}
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}
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if {[llength $argument_list] == 1 } {
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set options(project_name) [lindex $argument_list 0]
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if [string compare [file extension $options(project_name)] ""] {
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set project_name [file rootname $options(project_name)]
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}
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set project_name [file normalize $options(project_name)]
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} elseif { [llength $argument_list] == 2 } {
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set options(project_name) [lindex $argument_list 0]
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set options(rev) [lindex $argument_list 1]
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if [string compare [file extension $options(project_name)] ""] {
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set project_name [file rootname $options(project_name)]
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}
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if [string compare [file extension $options(c)] ""] {
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set revision_name [file rootname $options(c)]
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}
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set project_name [file normalize $options(project_name)]
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set revision_name [file normalize $options(rev)]
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} elseif { [ is_project_open ] } {
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set project_name $::quartus(project)
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set options(rev) $::quartus(settings)
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} else {
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post_message -type error "Project name is missing"
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post_message -type info [::cmdline::usage $::available_options $usage]
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post_message -type info "For more details, use \"quartus_sta --help\""
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qexit -error
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}
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# If this script is called from outside quartus_sta/map, it will re-launch itself in quartus_sta
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if { ![info exists quartus(nameofexecutable)] || ($quartus(nameofexecutable) != "quartus_sta" && $quartus(nameofexecutable) != "quartus_map") } {
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post_message -type info "Restarting in quartus_sta..."
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set cmd quartus_sta
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if { [info exists quartus(binpath)] } {
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set cmd [file join $quartus(binpath) $cmd]
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}
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if { [ is_project_open ] } {
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set project_name [ get_current_revision ]
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} elseif { ! [ string compare $project_name "" ] } {
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post_message -type error "Missing project_name argument"
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return 1
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}
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set output [ exec $cmd -t [ info script ] $project_name ]
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foreach line [split $output \n] {
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set type info
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set matched_line [ regexp {^\W*(Info|Extra Info|Warning|Critical Warning|Error): (.*)$} $line x type msg ]
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regsub " " $type _ type
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if { $matched_line } {
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post_message -type $type $msg
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} else {
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puts "$line"
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}
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}
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return 0
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}
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if { ! [ is_project_open ] } {
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if { ! [ string compare $project_name "" ] } {
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post_message -type error "Missing project_name argument"
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return 1
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}
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if {$options(c) == "#_ignore_#"} {
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project_open $project_name
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} else {
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project_open $project_name -revision $options(c)
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}
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}
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source "$script_dir/ddr3_p0_parameters.tcl"
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source "$script_dir/ddr3_p0_pin_map.tcl"
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set family_name [string tolower [regsub -all " +" [get_global_assignment -name FAMILY] ""]]
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#######################################
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# Check if user is using a SOC Device #
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#######################################
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set device_name [string tolower [regsub -all " +" [get_global_assignment -name DEVICE] ""]]
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set is_av_soc_device 0
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set is_speedgrade_i5 0
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set is_speedgrade_c5 0
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set soc_device_regexp "5as"
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set i5_regexp "i5"
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set c5_regexp "c5"
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if {[regexp $soc_device_regexp $device_name]} {
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set is_av_soc_device 1
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}
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if {[regexp $i5_regexp $device_name]} {
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set is_speedgrade_i5 1
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} elseif {[regexp $c5_regexp $device_name]} {
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set is_speedgrade_c5 1
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}
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##############################
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# Clean up stale assignments #
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##############################
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post_message -type info "Cleaning up stale assignments..."
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set asgn_types [ list IO_STANDARD INPUT_TERMINATION OUTPUT_TERMINATION CURRENT_STRENGTH_NEW DQ_GROUP TERMINATION_CONTROL_BLOCK ]
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foreach asgn_type $asgn_types {
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remove_all_instance_assignments -tag __$::GLOBAL_ddr3_p0_corename -name $asgn_type
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}
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if { ! [ timing_netlist_exist ] } {
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create_timing_netlist -post_map
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}
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#######################
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# #
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# ASSIGNMENTS SECTION #
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# #
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#######################
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# This is the main call to the netlist traversal routines
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# that will automatically find all pins and registers required
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# to apply pin settings.
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ddr3_p0_initialize_ddr_db ddr_db
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# If multiple instances of this core are present in the
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# design they will all be constrained through the
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# following loop
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set instances [ array names ddr_db ]
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foreach inst $instances {
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if { [ info exists pins ] } {
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# Clean-up stale content
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unset pins
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}
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array set pins $ddr_db($inst)
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if {$is_av_soc_device} {
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set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING ON
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}
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ddr3_p0_get_rzq_pins $inst all_rzq_pins
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# Set rzq pin I/O standard
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foreach rzq_pin $all_rzq_pins {
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set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard" -to $rzq_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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# 1.35V DDR3L pin assignments
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if { ! [ string compare $::GLOBAL_ddr3_p0_io_standard "SSTL-135" ] } {
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foreach dq_pin $pins(all_dq_pins) {
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set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard" -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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foreach dqs_pin [ concat $pins(dqs_pins) $pins(dqsn_pins) ] {
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_ddr3_p0_io_standard_differential" -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name D5_DELAY 4 -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name D6_DELAY 0 -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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foreach ck_pin [ concat $pins(ck_pins) $pins(ckn_pins) ] {
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_ddr3_p0_io_standard_differential" -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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if {$is_av_soc_device} {
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if {$is_speedgrade_i5} {
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set_instance_assignment -name D5_DELAY 5 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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} elseif {$is_speedgrade_c5} {
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set_instance_assignment -name D5_DELAY 10 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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} else {
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set_instance_assignment -name D5_DELAY 8 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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} else {
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set_instance_assignment -name D5_DELAY 2 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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}
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foreach ac_pin $pins(ac_wo_reset_pins) {
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set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard" -to $ac_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to $ac_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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foreach reset_pin $pins(reset_pins) {
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set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard" -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name BOARD_MODEL_FAR_PULLUP_R OPEN -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R OPEN -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name BOARD_MODEL_FAR_PULLDOWN_R OPEN -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R OPEN -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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foreach dm_pin $pins(dm_pins) {
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set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard" -to $dm_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to $dm_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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} else {
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# 1.5V DDR3 pin assignments
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foreach dq_pin $pins(all_dq_pins) {
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set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard CLASS I" -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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foreach dqs_pin [ concat $pins(dqs_pins) $pins(dqsn_pins) ] {
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_ddr3_p0_io_standard_differential CLASS I" -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name D5_DELAY 4 -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name D6_DELAY 0 -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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foreach ck_pin [ concat $pins(ck_pins) $pins(ckn_pins) ] {
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL $::GLOBAL_ddr3_p0_io_standard_differential CLASS I" -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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if {$is_av_soc_device} {
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if {$is_speedgrade_i5} {
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set_instance_assignment -name D5_DELAY 5 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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} elseif {$is_speedgrade_c5} {
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set_instance_assignment -name D5_DELAY 10 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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} else {
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set_instance_assignment -name D5_DELAY 8 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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} else {
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set_instance_assignment -name D5_DELAY 2 -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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}
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foreach ac_pin $pins(ac_wo_reset_pins) {
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set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard CLASS I" -to $ac_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to $ac_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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foreach reset_pin $pins(reset_pins) {
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set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard_cmos" -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to $reset_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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foreach dm_pin $pins(dm_pins) {
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set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard CLASS I" -to $dm_pin -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to $dm_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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}
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foreach refclk_pin $pins(pll_ref_clock) {
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if {![string compare [get_instance_assignment -to $refclk_pin -name IO_STANDARD] ""]} {
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set_instance_assignment -name IO_STANDARD "$::GLOBAL_ddr3_p0_io_standard" -to $refclk_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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}
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set ::GLOBAL_ddr3_p0_dqs_group_size_constraint $::GLOBAL_ddr3_p0_dqs_group_size
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if { $::GLOBAL_ddr3_p0_dqs_group_size == 8 } {
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set ::GLOBAL_ddr3_p0_dqs_group_size_constraint 9
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}
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set delay_chain_config FLEXIBLE_TIMING
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# Disable package skew compensation for data pins in timing analysis
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foreach dq_pin $pins(all_dq_pins) {
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set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $dq_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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foreach dm_pin $pins(dm_pins) {
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set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $dm_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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foreach dqs_pin [ concat $pins(dqs_pins) $pins(dqsn_pins) ] {
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set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $dqs_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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# Disable package skew compensation for address/command pins in timing analysis
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foreach ac_pin $pins(ac_pins) {
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set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $ac_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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foreach ck_pin [ concat $pins(ck_pins) $pins(ckn_pins) ] {
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set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to $ck_pin -tag __$::GLOBAL_ddr3_p0_corename
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}
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set seq_clks 2
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set qr_related_clks 0
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set dr_clk 0
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# Create the global and regional clocks
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# PLL clocks
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# Avalon Clock
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set pll_avl_clock [ ddr3_p0_get_pll_clock_name_for_acf $pins(pll_avl_clock) "pll_avl_clk" ]
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# Scan Chain Configuration CLock
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set pll_config_clock [ ddr3_p0_get_pll_clock_name_for_acf $pins(pll_config_clock) "pll_config_clk" ]
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if { $::GLOBAL_ddr3_p0_num_pll_clock == [ expr 5 + $seq_clks + $dr_clk + $qr_related_clks ] } {
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set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to $pll_avl_clock -tag __$::GLOBAL_ddr3_p0_corename
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set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to $pll_config_clock -tag __$::GLOBAL_ddr3_p0_corename
|
|
} else {
|
|
post_message -type critical_warning "Expected [ expr 5 + $seq_clks + $dr_clk + $qr_related_clks ] PLL clocks but found $::GLOBAL_ddr3_p0_num_pll_clock!"
|
|
}
|
|
|
|
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|ureset|phy_reset_mem_stable_n" -tag __$::GLOBAL_ddr3_p0_corename
|
|
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|ureset|phy_reset_n" -tag __$::GLOBAL_ddr3_p0_corename
|
|
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n" -tag __$::GLOBAL_ddr3_p0_corename
|
|
|
|
for {set i 0} {$i < $::GLOBAL_ddr3_p0_number_of_dqs_groups} {incr i 1} {
|
|
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|uio_pads|dq_ddio[$i].read_capture_clk_buffer" -tag __$::GLOBAL_ddr3_p0_corename
|
|
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|uread_datapath|reset_n_fifo_write_side[$i]" -tag __$::GLOBAL_ddr3_p0_corename
|
|
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "${inst}|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[$i]" -tag __$::GLOBAL_ddr3_p0_corename
|
|
}
|
|
|
|
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to $inst -tag __$::GLOBAL_ddr3_p0_corename
|
|
|
|
# Use direct compensation mode to minimize jitter
|
|
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "${inst}|pll0|fbout" -tag __$::GLOBAL_ddr3_p0_corename
|
|
}
|
|
|
|
ddr3_p0_dump_all_pins ddr_db
|
|
|
|
if { [ llength $quartus(args) ] > 1 } {
|
|
set param [lindex $quartus(args) 1]
|
|
|
|
if { [ string match -dump_static_pin_map $param ] } {
|
|
set filename "${::GLOBAL_ddr3_p0_corename}_static_pin_map.tcl"
|
|
|
|
ddr3_p0_dump_static_pin_map ddr_db $filename
|
|
}
|
|
}
|
|
|
|
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
|
|
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
|
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
|
|
|
set_global_assignment -name ECO_REGENERATE_REPORT ON
|