63 lines
1.9 KiB
Verilog
63 lines
1.9 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module ddr3_p0_reset_sync(
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reset_n,
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clk,
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reset_n_sync
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);
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parameter RESET_SYNC_STAGES = 4;
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parameter NUM_RESET_OUTPUT = 1;
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input reset_n;
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input clk;
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output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
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// identify the synchronizer chain so that Quartus can analyze metastability.
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// Since these resets are localized to the PHY alone, make them routed locally
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// to avoid using global networks.
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(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
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generate
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genvar i;
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for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
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begin: reset_stage
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always @(posedge clk or negedge reset_n)
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begin
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if (~reset_n)
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reset_reg[i] <= 1'b0;
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else
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begin
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if (i==0)
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reset_reg[i] <= 1'b1;
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else if (i < RESET_SYNC_STAGES)
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reset_reg[i] <= reset_reg[i-1];
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else
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reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
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end
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end
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end
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endgenerate
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assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
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endmodule
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