133 lines
2.4 KiB
Verilog
133 lines
2.4 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module sequencer_scc_acv_phase_decode
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# (parameter
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AVL_DATA_WIDTH = 32,
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DLL_DELAY_CHAIN_LENGTH = 8,
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USE_2X_DLL = "false"
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)
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(
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avl_writedata,
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dqse_phase
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);
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input [AVL_DATA_WIDTH - 1:0] avl_writedata;
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// Arria V and Cyclone V only have dqse_phase control
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// phase decoding.
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output [3:0] dqse_phase;
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reg [3:0] dqse_phase;
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generate
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if (USE_2X_DLL == "true")
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begin
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always @ (*) begin : decode_2x
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dqse_phase = 4'b0111;
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case (avl_writedata[2:0])
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3'b000:
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begin
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dqse_phase = 4'b0100;
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end
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3'b001:
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begin
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dqse_phase = 4'b0101;
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end
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3'b010:
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begin
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dqse_phase = 4'b0110;
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end
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3'b011:
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begin
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dqse_phase = 4'b0111;
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end
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3'b100:
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begin
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dqse_phase = 4'b1000;
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end
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3'b101:
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begin
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dqse_phase = 4'b1001;
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end
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3'b110:
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begin
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dqse_phase = 4'b1010;
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end
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3'b111:
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begin
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dqse_phase = 4'b1011;
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end
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default : begin end
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endcase
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end
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end
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else
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begin
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always @ (*) begin : decode
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// DQSE = 270
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dqse_phase = 4'b0110;
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case (avl_writedata[2:0])
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3'b000: // DQSE = 90
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begin
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dqse_phase = 4'b0010;
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end
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3'b001: // DQSE = 135
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begin
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dqse_phase = 4'b0011;
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end
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3'b010: // DQSE = 180
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begin
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dqse_phase = 4'b0100;
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end
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3'b011: // DQSE = 225
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begin
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dqse_phase = 4'b0101;
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end
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3'b100: // DQSE = 270
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begin
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dqse_phase = 4'b0110;
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end
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3'b101: // DQSE = 315
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begin
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dqse_phase = 4'b1111;
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end
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3'b110: // DQSE = 360
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begin
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dqse_phase = 4'b1000;
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end
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3'b111: // DQSE = 405
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begin
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dqse_phase = 4'b1001;
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end
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default : begin end
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endcase
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end
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end
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endgenerate
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endmodule
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