82 lines
2.5 KiB
Verilog
82 lines
2.5 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module sequencer_scc_reg_file (
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clock,
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data,
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rdaddress,
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wraddress,
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wren,
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q);
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parameter WIDTH = "";
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parameter DEPTH = "";
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input clock;
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input [WIDTH-1:0] data;
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input [DEPTH-1:0] rdaddress;
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input [DEPTH-1:0] wraddress;
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input wren;
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output [WIDTH-1:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 wren;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [WIDTH-1:0] sub_wire0;
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wire [WIDTH-1:0] q = sub_wire0[WIDTH-1:0];
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altdpram altdpram_component (
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.data (data),
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.outclock (),
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.rdaddress (rdaddress),
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.wren (wren),
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.inclock (clock),
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.wraddress (wraddress),
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.q (sub_wire0),
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.aclr (1'b0),
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.byteena (1'b1),
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.inclocken (1'b1),
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.outclocken (1'b1),
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.rdaddressstall (1'b0),
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.rden (1'b1),
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.wraddressstall (1'b0));
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defparam
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altdpram_component.indata_aclr = "OFF",
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altdpram_component.indata_reg = "INCLOCK",
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altdpram_component.intended_device_family = "Stratix IV",
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altdpram_component.lpm_type = "altdpram",
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altdpram_component.outdata_aclr = "OFF",
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altdpram_component.outdata_reg = "UNREGISTERED",
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altdpram_component.ram_block_type = "MLAB",
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altdpram_component.rdaddress_aclr = "OFF",
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altdpram_component.rdaddress_reg = "UNREGISTERED",
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altdpram_component.rdcontrol_aclr = "OFF",
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altdpram_component.rdcontrol_reg = "UNREGISTERED",
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altdpram_component.width = WIDTH,
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altdpram_component.widthad = DEPTH,
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altdpram_component.width_byteena = 1,
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altdpram_component.wraddress_aclr = "OFF",
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altdpram_component.wraddress_reg = "INCLOCK",
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altdpram_component.wrcontrol_aclr = "OFF",
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altdpram_component.wrcontrol_reg = "INCLOCK";
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endmodule
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