179 lines
3.8 KiB
Verilog
179 lines
3.8 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module sequencer_scc_sv_phase_decode
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# (parameter
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AVL_DATA_WIDTH = 32,
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DLL_DELAY_CHAIN_LENGTH = 6
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)
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(
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avl_writedata,
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dqsi_phase,
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dqs_phase,
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dq_phase,
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dqse_phase
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);
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input [AVL_DATA_WIDTH - 1:0] avl_writedata;
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output [2:0] dqsi_phase;
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output [6:0] dqs_phase;
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output [6:0] dq_phase;
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output [5:0] dqse_phase;
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reg [2:0] dqsi_phase;
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reg [6:0] dqs_phase;
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reg [6:0] dq_phase;
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reg [5:0] dqse_phase;
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always @ (*) begin
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dqsi_phase = 3'b010;
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dqs_phase = 7'b1110110;
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dq_phase = 7'b0110100;
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dqse_phase = 6'b000110;
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case (avl_writedata[4:0])
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5'b00000: // DQS = 180, DQ = 90, DQSE = 90
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begin
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dqs_phase = 7'b0010110;
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dq_phase = 7'b1000110;
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dqse_phase = 6'b000010;
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end
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5'b00001: // DQS = 225, DQ = 135, DQSE = 135
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begin
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dqs_phase = 7'b0110110;
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dq_phase = 7'b1100110;
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dqse_phase = 6'b000011;
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end
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5'b00010: // DQS = 270, DQ = 180, DQSE = 180
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begin
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dqs_phase = 7'b1010110;
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dq_phase = 7'b0010110;
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dqse_phase = 6'b000100;
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end
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5'b00011: // DQS = 315, DQ = 225, DQSE = 225
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begin
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dqs_phase = 7'b1110111;
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dq_phase = 7'b0110110;
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dqse_phase = 6'b000101;
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end
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5'b00100: // DQS = 360, DQ = 270, DQSE = 270
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begin
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dqs_phase = 7'b0000111;
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dq_phase = 7'b1010110;
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dqse_phase = 6'b000110;
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end
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5'b00101: // DQS = 405, DQ = 315, DQSE = 315
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begin
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dqs_phase = 7'b0100111;
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dq_phase = 7'b1110111;
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dqse_phase = 6'b001111;
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end
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5'b00110: // DQS = 450, DQ = 360, DQSE = 360
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begin
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dqs_phase = 7'b1001000;
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dq_phase = 7'b0000111;
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dqse_phase = 6'b001000;
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end
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5'b00111: // DQS = 495, DQ = 405, DQSE = 405
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begin
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dqs_phase = 7'b1101000;
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dq_phase = 7'b0100111;
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dqse_phase = 6'b001001;
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end
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5'b01000: // DQS = 540, DQ = 450
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begin
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dqs_phase = 7'b0011000;
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dq_phase = 7'b1001000;
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end
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5'b01001:
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begin
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dqs_phase = 7'b0111000;
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dq_phase = 7'b1101000;
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end
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5'b01010:
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begin
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dqs_phase = 7'b1011000;
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dq_phase = 7'b0011000;
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end
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5'b01011:
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begin
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dqs_phase = 7'b1111001;
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dq_phase = 7'b0111000;
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end
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5'b01100:
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begin
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dqs_phase = 7'b0001001;
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dq_phase = 7'b1011000;
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end
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5'b01101:
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begin
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dqs_phase = 7'b0101001;
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dq_phase = 7'b1111001;
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end
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5'b01110:
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begin
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dqs_phase = 7'b1001010;
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dq_phase = 7'b0001001;
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end
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5'b01111:
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begin
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dqs_phase = 7'b1101010;
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dq_phase = 7'b0101001;
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end
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5'b10000:
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begin
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dqs_phase = 7'b0011010;
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dq_phase = 7'b1001010;
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end
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5'b10001:
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begin
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dqs_phase = 7'b0111010;
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dq_phase = 7'b1101010;
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end
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5'b10010:
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begin
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dqs_phase = 7'b1011010;
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dq_phase = 7'b0011010;
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end
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5'b10011:
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begin
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dqs_phase = 7'b1111011;
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dq_phase = 7'b0111010;
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end
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5'b10100:
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begin
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dqs_phase = 7'b0001011;
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dq_phase = 7'b1011010;
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end
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5'b10101:
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begin
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dqs_phase = 7'b0101011;
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dq_phase = 7'b1111011;
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end
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default : begin end
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endcase
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end
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endmodule
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