220 lines
6.9 KiB
Systemverilog
220 lines
6.9 KiB
Systemverilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module sequencer_scc_sv_wrapper
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# (parameter
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DATAWIDTH = 24,
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IO_SDATA_BITS = 11,
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DQS_SDATA_BITS = 46,
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AVL_DATA_WIDTH = 32,
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DLL_DELAY_CHAIN_LENGTH = 6,
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DUAL_WRITE_CLOCK = 0
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)
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(
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reset_n_scc_clk,
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scc_clk,
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scc_dataout,
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scc_io_cfg,
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scc_dqs_cfg,
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scc_sr_dqsenable_delayctrl,
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scc_sr_dqsdisablen_delayctrl,
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scc_sr_multirank_delayctrl
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);
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input scc_clk;
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input reset_n_scc_clk;
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input [DATAWIDTH-1:0] scc_dataout;
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output [IO_SDATA_BITS - 1:0] scc_io_cfg;
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output [DQS_SDATA_BITS - 1:0] scc_dqs_cfg;
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output [7:0] scc_sr_dqsenable_delayctrl;
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output [7:0] scc_sr_dqsdisablen_delayctrl;
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output [7:0] scc_sr_multirank_delayctrl;
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typedef enum integer {
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SCC_ADDR_DQS_IN_DELAY = 'b0001,
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SCC_ADDR_DQS_EN_PHASE = 'b0010,
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SCC_ADDR_DQS_EN_DELAY = 'b0011,
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SCC_ADDR_DQDQS_OUT_PHASE= 'b0100,
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SCC_ADDR_OCT_OUT1_DELAY = 'b0101,
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SCC_ADDR_OCT_OUT2_DELAY = 'b0110,
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SCC_ADDR_IO_OUT1_DELAY = 'b0111,
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SCC_ADDR_IO_OUT2_DELAY = 'b1000,
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SCC_ADDR_IO_IN_DELAY = 'b1001
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} sdata_addr_t;
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wire [DATAWIDTH-1:0] scc_dataout;
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reg [IO_SDATA_BITS - 1:0] scc_io_cfg;
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reg [DQS_SDATA_BITS - 1:0] scc_dqs_cfg;
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reg [7:0] scc_sr_dqsenable_delayctrl;
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reg [7:0] scc_sr_dqsdisablen_delayctrl;
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reg [7:0] scc_sr_multirank_delayctrl;
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wire [2:0] dqsi_phase;
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wire [5:0] dqse_phase;
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wire [6:0] dqs_phase;
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wire [6:0] dq_phase;
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typedef bit [13:0] t_setting_mask;
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integer unsigned setting_offsets[1:9] = '{ 'd0, 'd12, 'd17, 'd25, 'd30, 'd36, 'd0, 'd6, 'd12 };
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t_setting_mask setting_masks [1:9] = '{ 'b0111111111111, 'b011111, 'b011111111, 'b011111, 'b0111111, 'b0111111, 'b0111111, 'b0111111, 'b0111111111111 };
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// decode phases
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sequencer_scc_sv_phase_decode # (
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.AVL_DATA_WIDTH (DATAWIDTH ),
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.DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH )
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) sequencer_scc_phase_decode_dqe_inst (
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.avl_writedata ((scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_PHASE]) & setting_masks[SCC_ADDR_DQS_EN_PHASE]),
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.dqsi_phase (dqsi_phase ),
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.dqse_phase (dqse_phase ),
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.dqs_phase(),
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.dq_phase()
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);
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sequencer_scc_sv_phase_decode # (
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.AVL_DATA_WIDTH (DATAWIDTH ),
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.DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH )
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) sequencer_scc_phase_decode_dqdqs_inst (
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.avl_writedata ((scc_dataout >> setting_offsets[SCC_ADDR_DQDQS_OUT_PHASE]) & setting_masks[SCC_ADDR_DQDQS_OUT_PHASE]),
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.dqs_phase (dqs_phase ),
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.dq_phase (dq_phase ),
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.dqsi_phase(),
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.dqse_phase()
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);
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always_ff @ (posedge scc_clk or negedge reset_n_scc_clk) begin
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if (~reset_n_scc_clk) begin
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scc_io_cfg <= '0;
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scc_dqs_cfg <= '0;
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scc_sr_dqsenable_delayctrl <= '0;
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scc_sr_dqsdisablen_delayctrl <= '0;
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scc_sr_multirank_delayctrl <= '0;
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scc_dqs_cfg[26] <= '1;
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scc_dqs_cfg[30] <= '1;
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scc_dqs_cfg[35] <= '1;
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scc_dqs_cfg[39] <= '1;
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scc_dqs_cfg[44] <= '1;
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scc_dqs_cfg[48] <= '1;
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scc_dqs_cfg[53] <= '1;
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scc_dqs_cfg[57] <= '1;
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scc_dqs_cfg[63] <= '1;
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end
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else begin
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scc_dqs_cfg <= '0;
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scc_dqs_cfg[26] <= '1;
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scc_dqs_cfg[30] <= '1;
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scc_dqs_cfg[35] <= '1;
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scc_dqs_cfg[39] <= '1;
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scc_dqs_cfg[44] <= '1;
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scc_dqs_cfg[48] <= '1;
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scc_dqs_cfg[53] <= '1;
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scc_dqs_cfg[57] <= '1;
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scc_dqs_cfg[63] <= '1;
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scc_dqs_cfg[88:87] <= dqsi_phase[1:0];
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scc_dqs_cfg[11:0] <= maskTo12Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_IN_DELAY]);
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scc_dqs_cfg[85:78] <= maskTo8Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]);
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scc_dqs_cfg[77:70] <= maskTo8Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]);
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scc_dqs_cfg[17:12] <= maskTo6Bits(scc_dataout >> setting_offsets[SCC_ADDR_OCT_OUT1_DELAY]);
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scc_dqs_cfg[23:18] <= maskTo6Bits(scc_dataout >> setting_offsets[SCC_ADDR_OCT_OUT2_DELAY]);
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scc_dqs_cfg[42:41] <= dqse_phase[1:0];
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scc_dqs_cfg[45] <= dqse_phase[2];
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scc_dqs_cfg[86] <= dqse_phase[3];
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if (DUAL_WRITE_CLOCK) begin
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scc_dqs_cfg[29:28] <= dqs_phase[6:5];
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scc_dqs_cfg[31] <= dqs_phase[4];
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scc_dqs_cfg[69] <= dqs_phase[0];
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scc_dqs_cfg[89] <= dqs_phase[0];
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scc_dqs_cfg[68:66] <= dqs_phase[3:1];
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scc_dqs_cfg[93:91] <= dqs_phase[3:1];
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scc_dqs_cfg[47:46] <= dqs_phase[6:5];
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scc_dqs_cfg[33:32] <= dqs_phase[6:5];
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scc_dqs_cfg[36] <= dqs_phase[4];
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scc_dqs_cfg[90] <= dqs_phase[0];
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scc_dqs_cfg[96:94] <= dqs_phase[3:1];
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scc_dqs_cfg[51:50] <= dqs_phase[6:5];
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scc_dqs_cfg[34] <= '1;
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scc_dqs_cfg[52] <= '1;
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end
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else begin
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scc_dqs_cfg[29:28] <= dqs_phase[6:5];
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scc_dqs_cfg[31] <= dqs_phase[4];
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scc_dqs_cfg[69] <= dqs_phase[0];
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scc_dqs_cfg[89] <= dqs_phase[0];
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scc_dqs_cfg[68:66] <= dqs_phase[3:1];
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scc_dqs_cfg[93:91] <= dqs_phase[3:1];
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scc_dqs_cfg[47:46] <= dqs_phase[6:5];
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scc_dqs_cfg[33:32] <= dq_phase[6:5];
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scc_dqs_cfg[36] <= dq_phase[4];
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scc_dqs_cfg[90] <= dq_phase[0];
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scc_dqs_cfg[96:94] <= dq_phase[3:1];
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scc_dqs_cfg[51:50] <= dq_phase[6:5];
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end
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scc_dqs_cfg[54] <= 1'b0;
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scc_dqs_cfg[49] <= 1'b0;
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scc_io_cfg[17:12] <= maskTo6Bits(scc_dataout >> setting_offsets[SCC_ADDR_IO_OUT1_DELAY]);
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scc_io_cfg[23:18] <= maskTo6Bits(scc_dataout >> setting_offsets[SCC_ADDR_IO_OUT2_DELAY]);
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scc_io_cfg[11:0] <= maskTo12Bits(scc_dataout >> setting_offsets[SCC_ADDR_IO_IN_DELAY]);
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scc_io_cfg[39:24] <= '0;
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scc_sr_dqsenable_delayctrl <= maskTo8Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]);
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scc_sr_dqsdisablen_delayctrl <= maskTo8Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]);
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scc_sr_multirank_delayctrl <= maskTo8Bits(scc_dataout >> setting_offsets[SCC_ADDR_DQS_EN_DELAY]);
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end
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end
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function[5:0] maskTo6Bits;
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input[DATAWIDTH-1:0] i;
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maskTo6Bits = i[5:0];
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endfunction
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function[7:0] maskTo8Bits;
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input[DATAWIDTH-1:0] i;
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maskTo8Bits = i[7:0];
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endfunction
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function[11:0] maskTo12Bits;
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input[DATAWIDTH-1:0] i;
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maskTo12Bits = i[11:0];
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endfunction
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endmodule
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