189 lines
4.5 KiB
VHDL
189 lines
4.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.wishbone_package.all;
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use work.crossbar_package.all;
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use work.dma_package.all;
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use work.test_slave_package.all;
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use work.clock_crossing_package.all;
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entity test is
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end test;
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architecture rtl of test is
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constant masters : natural := 3;
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constant slaves : natural := 3;
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signal m : wishbone_master_out;
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signal s : wishbone_master_in;
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signal intercon_slave_i : wishbone_slave_in_vector(masters-1 downto 0);
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signal intercon_slave_o : wishbone_slave_out_vector(masters-1 downto 0);
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signal intercon_master_i : wishbone_master_in_vector(slaves-1 downto 0);
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signal intercon_master_o : wishbone_master_out_vector(slaves-1 downto 0);
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signal ram_slave_i : wishbone_slave_in;
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signal ram_slave_o : wishbone_slave_out;
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signal rst : std_logic := '1';
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signal clk : std_logic := '0';
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signal ram_clk : std_logic := '0';
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procedure tick(signal clk : out std_logic) is
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begin
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wait for 20ns;
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clk <= '0';
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wait for 20ns;
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clk <= '1';
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wait for 0ns;
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end tick;
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procedure write (signal clk : out std_logic;
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signal m : out wishbone_master_out;
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signal r : in wishbone_master_in;
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constant a : in wishbone_address;
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constant d : in wishbone_data) is
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begin
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m.CYC <= '1';
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m.STB <= '1';
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m.SEL <= (others => '1');
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m.WE <= '1';
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m.ADR <= a;
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m.DAT <= d;
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tick(clk);
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while r.STALL = '1' loop
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tick(clk);
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end loop;
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m.STB <= '0';
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m.SEL <= (others => '0');
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m.ADR <= (others => '0');
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m.DAT <= (others => '0');
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m.WE <= '0';
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while r.ACK = '0' loop
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tick(clk);
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end loop;
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m.CYC <= '0';
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tick(clk);
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end write;
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begin
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intercon : crossbar
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generic map
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(
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masters => masters,
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slaves => slaves,
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async => false
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)
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port map
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(
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clk => clk,
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rst => rst,
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slave_i => intercon_slave_i,
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slave_o => intercon_slave_o,
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master_i => intercon_master_i,
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master_o => intercon_master_o,
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address => (0 => x"00000000",
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1 => x"10000000",
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2 => x"80000000"),
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mask => (0 => x"f0000000",
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1 => x"f0000000",
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2 => x"ffffffe0")
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);
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s0 : test_slave
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generic map
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(
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delay => 3
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)
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port map
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(
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clk => clk,
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rst => rst,
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slave_i => intercon_master_o(0),
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slave_o => intercon_master_i(0)
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);
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s1a : clock_crossing
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port map(
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rst => rst,
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slave_clk => clk,
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slave_i => intercon_master_o(1),
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slave_o => intercon_master_i(1),
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master_clk => ram_clk,
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master_i => ram_slave_o,
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master_o => ram_slave_i);
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s1r : test_slave
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generic map
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(
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delay => 1
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)
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port map
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(
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rst => rst,
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clk => ram_clk,
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slave_i => ram_slave_i,
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slave_o => ram_slave_o
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);
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dmac : dma
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generic map
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(
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logRingLen => 4
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)
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port map
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(
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clk => clk,
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rst => rst,
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w_master_i => intercon_slave_o(1),
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w_master_o => intercon_slave_i(1),
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r_master_i => intercon_slave_o(2),
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r_master_o => intercon_slave_i(2),
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slave_i => intercon_master_o(2),
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slave_o => intercon_master_i(2)
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);
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intercon_slave_i(0) <= m;
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s <= intercon_slave_o(0);
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main : process
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begin
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m <= (
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CYC => '0',
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STB => '0',
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ADR => (others => '0'),
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SEL => (others => '0'),
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WE => '0',
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DAT => (others => '0'));
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rst <= '1';
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tick(clk);
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tick(clk);
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tick(clk);
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rst <= '0';
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tick(clk);
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write(clk, m, s, x"80000000", x"10fffff0");
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write(clk, m, s, x"80000004", x"02345670");
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write(clk, m, s, x"80000008", x"00000004");
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write(clk, m, s, x"8000000c", x"00000004");
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write(clk, m, s, x"80000010", x"00000007");
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for i in 0 to 1024 loop
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tick(clk);
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end loop;
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end process;
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ram : process
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begin
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for i in 0 to 2048 loop
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wait for 13ns;
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ram_clk <= '0';
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wait for 13ns;
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ram_clk <= '1';
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end loop;
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end process;
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end rtl;
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