531 lines
21 KiB
Plaintext
531 lines
21 KiB
Plaintext
/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus Prime License Agreement,
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the Altera MegaCore Function License Agreement, or other
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applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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devices manufactured by Altera and sold by Altera or its
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authorized distributors. Please refer to the applicable
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agreement for further details.
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*/
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(text "pll_write_clk" (rect 165 819 408 1648)(font "Arial" (color 0 0 0)))
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(text "pll_avl_clk" (rect 165 883 396 1776)(font "Arial" (color 0 0 0)))
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(text "pll_config_clk" (rect 165 899 414 1808)(font "Arial" (color 0 0 0)))
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(text "afi_phy_clk" (rect 165 931 396 1872)(font "Arial" (color 0 0 0)))
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(text "pll_avl_phy_clk" (rect 165 947 420 1904)(font "Arial" (color 0 0 0)))
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(text " altera_mem_if_ddr3_emif " (rect 396 968 942 1946)(font "Arial" ))
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