142 lines
4.8 KiB
Verilog
142 lines
4.8 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
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// $Revision: #1 $
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// $Date: 2015/08/09 $
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// $Author: swbranch $
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ns
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module altera_avalon_st_clock_crosser(
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in_clk,
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in_reset,
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in_ready,
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in_valid,
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in_data,
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out_clk,
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out_reset,
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out_ready,
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out_valid,
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out_data
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);
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parameter SYMBOLS_PER_BEAT = 1;
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parameter BITS_PER_SYMBOL = 8;
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parameter FORWARD_SYNC_DEPTH = 2;
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parameter BACKWARD_SYNC_DEPTH = 2;
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parameter USE_OUTPUT_PIPELINE = 1;
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localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
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input in_clk;
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input in_reset;
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output in_ready;
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input in_valid;
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input [DATA_WIDTH-1:0] in_data;
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input out_clk;
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input out_reset;
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input out_ready;
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output out_valid;
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output [DATA_WIDTH-1:0] out_data;
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// Data is guaranteed valid by control signal clock crossing. Cut data
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// buffer false path.
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(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
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reg [DATA_WIDTH-1:0] out_data_buffer;
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reg in_data_toggle;
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wire in_data_toggle_returned;
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wire out_data_toggle;
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reg out_data_toggle_flopped;
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wire take_in_data;
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wire out_data_taken;
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wire out_valid_internal;
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wire out_ready_internal;
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assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
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assign take_in_data = in_valid & in_ready;
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assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
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assign out_data_taken = out_ready_internal & out_valid_internal;
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always @(posedge in_clk or posedge in_reset) begin
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if (in_reset) begin
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in_data_buffer <= {DATA_WIDTH{1'b0}};
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in_data_toggle <= 1'b0;
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end else begin
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if (take_in_data) begin
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in_data_toggle <= ~in_data_toggle;
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in_data_buffer <= in_data;
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end
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end //in_reset
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end //in_clk always block
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always @(posedge out_clk or posedge out_reset) begin
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if (out_reset) begin
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out_data_toggle_flopped <= 1'b0;
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out_data_buffer <= {DATA_WIDTH{1'b0}};
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end else begin
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out_data_buffer <= in_data_buffer;
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if (out_data_taken) begin
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out_data_toggle_flopped <= out_data_toggle;
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end
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end //end if
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end //out_clk always block
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altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
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.clk(out_clk),
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.reset_n(~out_reset),
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.din(in_data_toggle),
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.dout(out_data_toggle)
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);
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altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
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.clk(in_clk),
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.reset_n(~in_reset),
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.din(out_data_toggle_flopped),
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.dout(in_data_toggle_returned)
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);
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generate if (USE_OUTPUT_PIPELINE == 1) begin
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altera_avalon_st_pipeline_base
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#(
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.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
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.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
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) output_stage (
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.clk(out_clk),
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.reset(out_reset),
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.in_ready(out_ready_internal),
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.in_valid(out_valid_internal),
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.in_data(out_data_buffer),
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.out_ready(out_ready),
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.out_valid(out_valid),
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.out_data(out_data)
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);
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end else begin
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assign out_valid = out_valid_internal;
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assign out_ready_internal = out_ready;
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assign out_data = out_data_buffer;
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end
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endgenerate
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endmodule
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