190 lines
6.8 KiB
Systemverilog
190 lines
6.8 KiB
Systemverilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_burst_adapter/new_source/altera_default_burst_converter.sv#1 $
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// $Revision: #1 $
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// $Date: 2015/08/09 $
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// $Author: swbranch $
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// --------------------------------------------
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// Default Burst Converter
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// Notes:
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// 1) If burst type FIXED and slave is AXI,
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// passthrough the transaction.
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// 2) Else, converts burst into non-bursting
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// transactions (length of 1).
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// --------------------------------------------
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`timescale 1 ns / 1 ns
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module altera_default_burst_converter
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#(
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parameter PKT_BURST_TYPE_W = 2,
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parameter PKT_BURSTWRAP_W = 5,
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parameter PKT_ADDR_W = 12,
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parameter PKT_BURST_SIZE_W = 3,
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parameter IS_AXI_SLAVE = 0,
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parameter LEN_W = 2
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)
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(
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input clk,
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input reset,
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input enable,
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input [PKT_BURST_TYPE_W - 1 : 0] in_bursttype,
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input [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_reg,
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input [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_value,
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input [PKT_ADDR_W - 1 : 0] in_addr,
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input [PKT_ADDR_W - 1 : 0] in_addr_reg,
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input [LEN_W - 1 : 0] in_len,
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input [PKT_BURST_SIZE_W - 1 : 0] in_size_value,
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input in_is_write,
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output reg [PKT_ADDR_W - 1 : 0] out_addr,
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output reg [LEN_W - 1 : 0] out_len,
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output reg new_burst
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);
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// ---------------------------------------------------
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// AXI Burst Type Encoding
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// ---------------------------------------------------
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typedef enum bit [1:0]
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{
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FIXED = 2'b00,
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INCR = 2'b01,
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WRAP = 2'b10,
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RESERVED = 2'b11
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} AxiBurstType;
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// -------------------------------------------
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// Internal Signals
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// -------------------------------------------
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wire [LEN_W - 1 : 0] unit_len = {{LEN_W - 1 {1'b0}}, 1'b1};
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reg [LEN_W - 1 : 0] next_len;
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reg [LEN_W - 1 : 0] remaining_len;
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reg [PKT_ADDR_W - 1 : 0] next_incr_addr;
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reg [PKT_ADDR_W - 1 : 0] incr_wrapped_addr;
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reg [PKT_ADDR_W - 1 : 0] extended_burstwrap_value;
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reg [PKT_ADDR_W - 1 : 0] addr_incr_variable_size_value;
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// -------------------------------------------
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// Byte Count Converter
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// -------------------------------------------
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// Avalon Slave: Read/Write, the out_len is always 1 (unit_len).
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// AXI Slave: Read/Write, the out_len is always the in_len (pass through) of a given cycle.
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// If bursttype RESERVED, out_len is always 1 (unit_len).
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generate if (IS_AXI_SLAVE == 1)
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begin : axi_slave_out_len
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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out_len <= {LEN_W{1'b0}};
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end
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else if (enable) begin
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out_len <= (in_bursttype == FIXED) ? in_len : unit_len;
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end
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end
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end
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else // IS_AXI_SLAVE == 0
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begin : non_axi_slave_out_len
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always_comb begin
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out_len = unit_len;
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end
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end
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endgenerate
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always_comb begin : proc_extend_burstwrap
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extended_burstwrap_value = {{(PKT_ADDR_W - PKT_BURSTWRAP_W){in_burstwrap_reg[PKT_BURSTWRAP_W - 1]}}, in_burstwrap_value};
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addr_incr_variable_size_value = {{(PKT_ADDR_W - 1){1'b0}}, 1'b1} << in_size_value;
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end
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// -------------------------------------------
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// Address Converter
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// -------------------------------------------
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// Write: out_addr = in_addr at every cycle (pass through).
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// Read: out_addr = in_addr at every new_burst. Subsequent addresses calculated by converter.
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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next_incr_addr <= {PKT_ADDR_W{1'b0}};
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out_addr <= {PKT_ADDR_W{1'b0}};
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end
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else if (enable) begin
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next_incr_addr <= next_incr_addr + addr_incr_variable_size_value;
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if (new_burst) begin
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next_incr_addr <= in_addr + addr_incr_variable_size_value;
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end
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out_addr <= incr_wrapped_addr;
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end
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end
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always_comb begin
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incr_wrapped_addr = in_addr;
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if (!new_burst) begin
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// This formula calculates addresses of WRAP bursts and works perfectly fine for other burst types too.
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incr_wrapped_addr = (in_addr_reg & ~extended_burstwrap_value) | (next_incr_addr & extended_burstwrap_value);
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end
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end
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// -------------------------------------------
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// Control Signals
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// -------------------------------------------
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// Determine the min_len.
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// 1) FIXED read to AXI slave: One-time passthrough, therefore the min_len == in_len.
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// 2) FIXED write to AXI slave: min_len == 1.
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// 3) FIXED read/write to Avalon slave: min_len == 1.
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// 4) RESERVED read/write to AXI/Avalon slave: min_len == 1.
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wire [LEN_W - 1 : 0] min_len;
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generate if (IS_AXI_SLAVE == 1)
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begin : axi_slave_min_len
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assign min_len = (!in_is_write && (in_bursttype == FIXED)) ? in_len : unit_len;
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end
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else // IS_AXI_SLAVE == 0
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begin : non_axi_slave_min_len
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assign min_len = unit_len;
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end
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endgenerate
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// last_beat calculation.
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wire last_beat = (remaining_len == min_len);
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// next_len calculation.
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always_comb begin
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remaining_len = in_len;
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if (!new_burst) remaining_len = next_len;
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end
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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next_len <= 1'b0;
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end
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else if (enable) begin
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next_len <= remaining_len - unit_len;
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end
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end
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// new_burst calculation.
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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new_burst <= 1'b1;
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end
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else if (enable) begin
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new_burst <= last_beat;
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end
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end
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endmodule
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