118 lines
3.2 KiB
Systemverilog
118 lines
3.2 KiB
Systemverilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module altera_mem_if_sequencer_rst
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(
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clk,
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rst,
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clken_out,
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reset_out
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);
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timeunit 1ns;
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timeprecision 1ps;
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parameter DEPTH = 2;
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parameter CLKEN_LAGS_RESET = 0;
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localparam EARLY_RST_TAP = (CLKEN_LAGS_RESET != 0) ? 0 : 1;
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input clk;
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input rst;
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output clken_out;
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output reset_out;
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(*preserve*) reg [2: 0] altera_reset_synchronizer_int_chain;
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wire w_sync_rst_input;
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reg [(DEPTH-1): 0] r_sync_rst_chain;
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reg r_sync_rst_dly;
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reg r_sync_rst;
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reg r_early_rst;
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assign w_sync_rst_input = altera_reset_synchronizer_int_chain[2];
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assign clken_out =~r_early_rst;
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assign reset_out = r_sync_rst;
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initial
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begin
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altera_reset_synchronizer_int_chain <= '1;
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end
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always @(posedge clk)
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begin
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altera_reset_synchronizer_int_chain[2:0]
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<= {altera_reset_synchronizer_int_chain[1:0], ~rst};
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end
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initial
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begin
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r_sync_rst_chain <= {DEPTH{1'b1}};
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end
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always @(posedge clk)
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begin
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if (w_sync_rst_input == 1'b1)
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begin
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r_sync_rst_chain <= {DEPTH{1'b1}};
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end
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else
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begin
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r_sync_rst_chain <= {1'b0, r_sync_rst_chain[DEPTH-1:1]};
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end
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end
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initial
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begin
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r_sync_rst_dly <= 1'b1;
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r_sync_rst <= 1'b1;
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r_early_rst <= 1'b1;
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end
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always @(posedge clk)
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begin
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r_sync_rst_dly <= r_sync_rst_chain[DEPTH-1];
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case ({r_sync_rst_dly, r_sync_rst_chain[1], r_sync_rst})
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3'b000: r_sync_rst <= 1'b0;
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3'b001: r_sync_rst <= 1'b0;
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3'b010: r_sync_rst <= 1'b0;
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3'b011: r_sync_rst <= 1'b1;
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3'b100: r_sync_rst <= 1'b1;
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3'b101: r_sync_rst <= 1'b1;
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3'b110: r_sync_rst <= 1'b1;
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3'b111: r_sync_rst <= 1'b1;
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default: r_sync_rst <= 1'b1;
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endcase
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case ({r_sync_rst_chain[DEPTH-1], r_sync_rst_chain[EARLY_RST_TAP]})
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2'b00: r_early_rst <= 1'b0;
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2'b01: r_early_rst <= 1'b1;
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2'b10: r_early_rst <= 1'b0;
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2'b11: r_early_rst <= 1'b1;
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default: r_early_rst <= 1'b1;
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endcase
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end
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endmodule
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