320 lines
12 KiB
Verilog
320 lines
12 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// (C) 2001-2013 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
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// $Revision: #1 $
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// $Date: 2015/08/09 $
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// $Author: swbranch $
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// --------------------------------------
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// Reset controller
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//
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// Combines all the input resets and synchronizes
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// the result to the clk.
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// ACDS13.1 - Added reset request as part of reset sequencing
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// --------------------------------------
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`timescale 1 ns / 1 ns
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module altera_reset_controller
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#(
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parameter NUM_RESET_INPUTS = 6,
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parameter USE_RESET_REQUEST_IN0 = 0,
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parameter USE_RESET_REQUEST_IN1 = 0,
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parameter USE_RESET_REQUEST_IN2 = 0,
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parameter USE_RESET_REQUEST_IN3 = 0,
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parameter USE_RESET_REQUEST_IN4 = 0,
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parameter USE_RESET_REQUEST_IN5 = 0,
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parameter USE_RESET_REQUEST_IN6 = 0,
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parameter USE_RESET_REQUEST_IN7 = 0,
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parameter USE_RESET_REQUEST_IN8 = 0,
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parameter USE_RESET_REQUEST_IN9 = 0,
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parameter USE_RESET_REQUEST_IN10 = 0,
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parameter USE_RESET_REQUEST_IN11 = 0,
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parameter USE_RESET_REQUEST_IN12 = 0,
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parameter USE_RESET_REQUEST_IN13 = 0,
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parameter USE_RESET_REQUEST_IN14 = 0,
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parameter USE_RESET_REQUEST_IN15 = 0,
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parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
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parameter SYNC_DEPTH = 2,
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parameter RESET_REQUEST_PRESENT = 0,
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parameter RESET_REQ_WAIT_TIME = 3,
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parameter MIN_RST_ASSERTION_TIME = 11,
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parameter RESET_REQ_EARLY_DSRT_TIME = 4,
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parameter ADAPT_RESET_REQUEST = 0
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)
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(
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// --------------------------------------
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// We support up to 16 reset inputs, for now
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// --------------------------------------
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input reset_in0,
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input reset_in1,
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input reset_in2,
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input reset_in3,
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input reset_in4,
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input reset_in5,
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input reset_in6,
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input reset_in7,
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input reset_in8,
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input reset_in9,
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input reset_in10,
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input reset_in11,
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input reset_in12,
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input reset_in13,
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input reset_in14,
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input reset_in15,
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input reset_req_in0,
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input reset_req_in1,
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input reset_req_in2,
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input reset_req_in3,
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input reset_req_in4,
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input reset_req_in5,
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input reset_req_in6,
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input reset_req_in7,
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input reset_req_in8,
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input reset_req_in9,
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input reset_req_in10,
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input reset_req_in11,
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input reset_req_in12,
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input reset_req_in13,
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input reset_req_in14,
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input reset_req_in15,
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input clk,
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output reg reset_out,
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output reg reset_req
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);
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// Always use async reset synchronizer if reset_req is used
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localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
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// --------------------------------------
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// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
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// --------------------------------------
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localparam MIN_METASTABLE = 3;
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localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
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localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
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localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
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MIN_RST_ASSERTION_TIME + 1 :
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(
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(MIN_RST_ASSERTION_TIME > LARGER)?
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MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
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MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
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);
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localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
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// --------------------------------------
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wire merged_reset;
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wire merged_reset_req_in;
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wire reset_out_pre;
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wire reset_req_pre;
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// Registers and Interconnect
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(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
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reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
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reg r_sync_rst;
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reg r_early_rst;
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// --------------------------------------
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// "Or" all the input resets together
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// --------------------------------------
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assign merged_reset = (
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reset_in0 |
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reset_in1 |
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reset_in2 |
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reset_in3 |
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reset_in4 |
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reset_in5 |
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reset_in6 |
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reset_in7 |
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reset_in8 |
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reset_in9 |
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reset_in10 |
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reset_in11 |
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reset_in12 |
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reset_in13 |
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reset_in14 |
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reset_in15
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);
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assign merged_reset_req_in = (
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( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
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( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
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( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
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( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
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( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
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( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
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( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
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( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
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( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
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( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
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( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
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( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
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( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
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( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
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( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
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( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
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);
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// --------------------------------------
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// And if required, synchronize it to the required clock domain,
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// with the correct synchronization type
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// --------------------------------------
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generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
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assign reset_out_pre = merged_reset;
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assign reset_req_pre = merged_reset_req_in;
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end else begin
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altera_reset_synchronizer
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#(
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.DEPTH (SYNC_DEPTH),
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.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
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)
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alt_rst_sync_uq1
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(
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.clk (clk),
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.reset_in (merged_reset),
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.reset_out (reset_out_pre)
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);
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altera_reset_synchronizer
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#(
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.DEPTH (SYNC_DEPTH),
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.ASYNC_RESET(0)
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)
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alt_rst_req_sync_uq1
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(
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.clk (clk),
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.reset_in (merged_reset_req_in),
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.reset_out (reset_req_pre)
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);
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end
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endgenerate
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generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
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( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
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always @* begin
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reset_out = reset_out_pre;
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reset_req = reset_req_pre;
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end
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end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
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wire reset_out_pre2;
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altera_reset_synchronizer
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#(
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.DEPTH (SYNC_DEPTH+1),
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.ASYNC_RESET(0)
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)
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alt_rst_sync_uq2
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(
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.clk (clk),
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.reset_in (reset_out_pre),
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.reset_out (reset_out_pre2)
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);
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always @* begin
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reset_out = reset_out_pre2;
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reset_req = reset_req_pre;
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end
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end
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else begin
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// 3-FF Metastability Synchronizer
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initial
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begin
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altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
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end
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always @(posedge clk)
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begin
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altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
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{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
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end
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// Synchronous reset pipe
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initial
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begin
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r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
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end
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always @(posedge clk)
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begin
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if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
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begin
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r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
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end
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else
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begin
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r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
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end
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end
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// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
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// matches the early input.
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always @(posedge clk)
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begin
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case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
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3'b000: r_sync_rst <= 1'b0; // Not reset
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3'b001: r_sync_rst <= 1'b0;
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3'b010: r_sync_rst <= 1'b0;
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3'b011: r_sync_rst <= 1'b1;
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3'b100: r_sync_rst <= 1'b1;
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3'b101: r_sync_rst <= 1'b1;
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3'b110: r_sync_rst <= 1'b1;
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3'b111: r_sync_rst <= 1'b1; // In Reset
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default: r_sync_rst <= 1'b1;
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endcase
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case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
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2'b00: r_early_rst <= 1'b0; // Not reset
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2'b01: r_early_rst <= 1'b1; // Coming out of reset
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2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
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2'b11: r_early_rst <= 1'b1; // Held in reset
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default: r_early_rst <= 1'b1;
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endcase
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end
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always @* begin
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reset_out = r_sync_rst;
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reset_req = r_early_rst;
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end
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end
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endgenerate
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endmodule
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