113 lines
4.0 KiB
Systemverilog
113 lines
4.0 KiB
Systemverilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// (C) 2001-2013 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/13.1/ip/.../avalon-st_timing_adapter.sv.terp#1 $
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// $Revision: #1 $
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// $Date: 2013/09/27 $
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// $Author: dmunday, korthner $
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// --------------------------------------------------------------------------------
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//| Avalon Streaming Timing Adapter
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// --------------------------------------------------------------------------------
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`timescale 1ns / 100ps
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// ------------------------------------------
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// Generation parameters:
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// output_name: ddr3_dmaster_timing_adt
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// in_use_ready: false
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// out_use_ready: true
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// in_use_valid: true
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// out_use_valid: true
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// use_packets: false
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// use_empty: 0
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// empty_width: 0
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// data_width: 8
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// channel_width: 0
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// error_width: 0
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// in_ready_latency: 0
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// out_ready_latency: 0
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// in_payload_width: 8
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// out_payload_width: 8
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// in_payload_map: in_data
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// out_payload_map: out_data
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// ------------------------------------------
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module ddr3_dmaster_timing_adt
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(
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input in_valid,
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input [8-1: 0] in_data,
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// Interface: out
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input out_ready,
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output reg out_valid,
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output reg [8-1: 0] out_data,
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// Interface: clk
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input clk,
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// Interface: reset
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input reset_n
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/*AUTOARG*/);
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// ---------------------------------------------------------------------
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//| Signal Declarations
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// ---------------------------------------------------------------------
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reg [8-1:0] in_payload;
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reg [8-1:0] out_payload;
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reg [1-1:0] ready;
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reg in_ready;
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// synthesis translate_off
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always @(negedge in_ready) begin
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$display("%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.");
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end
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// synthesis translate_on
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// ---------------------------------------------------------------------
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//| Payload Mapping
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// ---------------------------------------------------------------------
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always @* begin
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in_payload = {in_data};
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{out_data} = out_payload;
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end
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// ---------------------------------------------------------------------
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//| Ready & valid signals.
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// ---------------------------------------------------------------------
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always_comb begin
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ready[0] = out_ready;
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out_valid = in_valid;
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out_payload = in_payload;
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in_ready = ready[0];
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end
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endmodule
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