90 lines
2.3 KiB
Verilog
90 lines
2.3 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module ddr3_p0_generic_ddio(
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datain,
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halfratebypass,
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dataout,
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clk_hr,
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clk_fr
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);
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parameter WIDTH = 1;
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localparam DATA_IN_WIDTH = 4 * WIDTH;
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localparam DATA_OUT_WIDTH = WIDTH;
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input [DATA_IN_WIDTH-1:0] datain;
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input halfratebypass;
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input [WIDTH-1:0] clk_hr;
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input [WIDTH-1:0] clk_fr;
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output [DATA_OUT_WIDTH-1:0] dataout;
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generate
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genvar pin;
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for (pin = 0; pin < WIDTH; pin = pin + 1)
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begin:acblock
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wire fr_data_hi;
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wire fr_data_lo;
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cyclonev_ddio_out
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#(
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.half_rate_mode("true"),
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.use_new_clocking_model("true"),
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.async_mode("none")
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) hr_to_fr_hi (
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.datainhi(datain[pin * 4]),
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.datainlo(datain[pin * 4 + 2]),
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.dataout(fr_data_hi),
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.clkhi (clk_hr[pin]),
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.clklo (clk_hr[pin]),
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.hrbypass(halfratebypass),
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.muxsel (clk_hr[pin])
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);
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cyclonev_ddio_out
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#(
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.half_rate_mode("true"),
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.use_new_clocking_model("true"),
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.async_mode("none")
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) hr_to_fr_lo (
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.datainhi(datain[pin * 4 + 1]),
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.datainlo(datain[pin * 4 + 3]),
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.dataout(fr_data_lo),
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.clkhi (clk_hr[pin]),
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.clklo (clk_hr[pin]),
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.hrbypass(halfratebypass),
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.muxsel (clk_hr[pin])
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);
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cyclonev_ddio_out
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#(
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.async_mode("none"),
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.half_rate_mode("false"),
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.sync_mode("none"),
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.use_new_clocking_model("true")
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) ddio_out (
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.datainhi(fr_data_hi),
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.datainlo(fr_data_lo),
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.dataout(dataout[pin]),
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.clkhi (clk_fr[pin]),
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.clklo (clk_fr[pin]),
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.muxsel (clk_fr[pin])
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);
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end
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endgenerate
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endmodule
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