475 lines
11 KiB
Verilog
475 lines
11 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module sequencer_scc_siii_phase_decode
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# (parameter
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AVL_DATA_WIDTH = 32,
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DLL_DELAY_CHAIN_LENGTH = 6
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)
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(
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avl_writedata,
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dqsi_phase,
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dqs_phase,
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dq_phase,
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dqse_phase
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);
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input [AVL_DATA_WIDTH - 1:0] avl_writedata;
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output [2:0] dqsi_phase;
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output [6:0] dqs_phase;
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output [6:0] dq_phase;
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output [5:0] dqse_phase;
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// phase decoding.
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reg [2:0] dqsi_phase;
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reg [6:0] dqs_phase;
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reg [6:0] dq_phase;
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reg [5:0] dqse_phase;
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// decode phases
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always @ (*) begin
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dqsi_phase = 0;
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dqs_phase = 0;
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dq_phase = 0;
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dqse_phase = 0;
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case (DLL_DELAY_CHAIN_LENGTH)
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6: begin
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// DQSin = 60, DQS = 180, DQ = 120, DQSE = 120
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dqsi_phase = 3'b000;
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dqs_phase = 7'b0010100;
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dq_phase = 7'b0001100;
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dqse_phase = 6'b001000;
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case (avl_writedata[4:0])
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5'b00000: // DQS = 180, DQ = 120, DQSE = 120
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begin
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dqs_phase = 7'b0010100;
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dq_phase = 7'b0001100;
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dqse_phase = 6'b001000;
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end
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5'b00001: // DQS = 240, DQ = 180, DQSE = 180
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begin
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dqs_phase = 7'b0011100;
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dq_phase = 7'b0010100;
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dqse_phase = 6'b001100;
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end
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5'b00010: // DQS = 300, DQ = 240, DQSE = 240
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begin
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dqs_phase = 7'b0100110;
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dq_phase = 7'b0011100;
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dqse_phase = 6'b000110;
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end
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5'b00011: // DQS = 360, DQ = 300, DQSE = 300
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begin
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dqs_phase = 7'b0010010;
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dq_phase = 7'b0001010;
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dqse_phase = 6'b001011;
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end
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5'b00100: // DQS = 420, DQ = 360, DQSE = 360
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begin
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dqs_phase = 7'b0011010;
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dq_phase = 7'b0010010;
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dqse_phase = 6'b001111;
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end
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5'b00101: // DQS = 480, DQ = 420, DQSE = 420
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begin
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dqs_phase = 7'b0100001;
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dq_phase = 7'b0011010;
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dqse_phase = 6'b000101;
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end
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5'b00110: // DQS = 540, DQ = 480
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begin
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dqs_phase = 7'b0010101;
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dq_phase = 7'b0001101;
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end
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5'b00111: // DQS = 600, DQ = 540
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begin
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dqs_phase = 7'b0011101;
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dq_phase = 7'b0010101;
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end
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5'b01000: // DQS = 660, DQ = 600
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begin
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dqs_phase = 7'b0100111;
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dq_phase = 7'b0011101;
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end
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5'b01001: // DQS = 720, DQ = 660
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begin
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dqs_phase = 7'b0010011;
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dq_phase = 7'b0001011;
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end
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5'b01010: // DQS = 780, DQ = 720
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begin
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dqs_phase = 7'b0011011;
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dq_phase = 7'b0010011;
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end
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default : begin end
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endcase
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end
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8: begin
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// DQSin = 90, DQS = 180, DQ = 90, DQSE = 90
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dqsi_phase = 3'b001;
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dqs_phase = 7'b0010100;
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dq_phase = 7'b0000100;
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dqse_phase = 6'b001000;
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case (avl_writedata[4:0])
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5'b00000: // DQS = 180, DQ = 90, DQSE = 90
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begin
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dqs_phase = 7'b0010100;
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dq_phase = 7'b0000100;
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dqse_phase = 6'b001000;
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end
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5'b00001: // DQS = 225, DQ = 135, DQSE = 135
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begin
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dqs_phase = 7'b0011100;
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dq_phase = 7'b0001100;
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dqse_phase = 6'b001100;
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end
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5'b00010: // DQS = 270, DQ = 180, DQSE = 180
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begin
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dqs_phase = 7'b0100100;
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dq_phase = 7'b0010100;
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dqse_phase = 6'b010000;
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end
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5'b00011: // DQS = 315, DQ = 225, DQSE = 225
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begin
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dqs_phase = 7'b0101110;
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dq_phase = 7'b0011100;
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dqse_phase = 6'b000110;
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end
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5'b00100: // DQS = 360, DQ = 270, DQSE = 270
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begin
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dqs_phase = 7'b0010010;
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dq_phase = 7'b0000000;
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dqse_phase = 6'b001010;
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end
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5'b00101: // DQS = 405, DQ = 315, DQSE = 315
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begin
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dqs_phase = 7'b0011010;
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dq_phase = 7'b0001010;
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dqse_phase = 6'b001111;
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end
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5'b00110: // DQS = 450, DQ = 360, DQSE = 360
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begin
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dqs_phase = 7'b0100010;
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dq_phase = 7'b0010010;
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dqse_phase = 6'b010011;
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end
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5'b00111: // DQS = 495, DQ = 405, DQSE = 405
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begin
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dqs_phase = 7'b0101001;
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dq_phase = 7'b0011010;
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dqse_phase = 6'b000101;
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end
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5'b01000: // DQS = 540, DQ = 450
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begin
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dqs_phase = 7'b0010101;
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dq_phase = 7'b0000110;
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end
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5'b01001: // DQS = 585, DQ = 495
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begin
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dqs_phase = 7'b0011101;
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dq_phase = 7'b0001101;
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end
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5'b01010: // DQS = 630, DQ = 540
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begin
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dqs_phase = 7'b0100101;
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dq_phase = 7'b0010101;
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end
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5'b01011: // DQS = 675, DQ = 585
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begin
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dqs_phase = 7'b0101111;
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dq_phase = 7'b0011101;
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end
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5'b01100: // DQS = 720, DQ = 630
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begin
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dqs_phase = 7'b0010011;
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dq_phase = 7'b0000001;
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end
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5'b01101: // DQS = 765, DQ = 675
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begin
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dqs_phase = 7'b0011011;
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dq_phase = 7'b0001011;
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end
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5'b01110: // DQS = 810, DQ = 720
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begin
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dqs_phase = 7'b0100011;
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dq_phase = 7'b0010011;
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end
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default : begin end
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endcase
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end
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10: begin
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// DQSin = 72, DQS = 180, DQ = 108, DQSE = 108
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dqsi_phase = 3'b001;
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dqs_phase = 7'b0010100;
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dq_phase = 7'b0000100;
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dqse_phase = 6'b001100;
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case (avl_writedata[4:0])
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5'b00000: // DQS = 180, DQ = 108, DQSE = 108
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begin
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dqs_phase = 7'b0010100;
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dq_phase = 7'b0000100;
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dqse_phase = 6'b001100;
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end
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5'b00001: // DQS = 216, DQ = 144, DQSE = 144
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begin
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dqs_phase = 7'b0011100;
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dq_phase = 7'b0001100;
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dqse_phase = 6'b010000;
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end
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5'b00010: // DQS = 252, DQ = 180, DQSE = 180
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begin
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dqs_phase = 7'b0100100;
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dq_phase = 7'b0010100;
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dqse_phase = 6'b010100;
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end
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5'b00011: // DQS = 288, DQ = 216, DQSE = 216
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begin
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dqs_phase = 7'b0101110;
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dq_phase = 7'b0011100;
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dqse_phase = 6'b000110;
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end
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5'b00100: // DQS = 324, DQ = 252, DQSE = 252
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begin
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dqs_phase = 7'b0110110;
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dq_phase = 7'b0100100;
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dqse_phase = 6'b001010;
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end
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5'b00101: // DQS = 360, DQ = 288, DQSE = 288
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begin
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dqs_phase = 7'b0010010;
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dq_phase = 7'b0000010;
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dqse_phase = 6'b001111;
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end
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5'b00110: // DQS = 396, DQ = 324, DQSE = 324
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begin
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dqs_phase = 7'b0011010;
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dq_phase = 7'b0001010;
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dqse_phase = 6'b010011;
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end
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5'b00111: // DQS = 432, DQ = 360, DQSE = 360
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begin
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dqs_phase = 7'b0100010;
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dq_phase = 7'b0010010;
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dqse_phase = 6'b010111;
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end
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5'b01000: // DQS = 468, DQ = 396, DQSE = 396
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begin
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dqs_phase = 7'b0101001;
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dq_phase = 7'b0011010;
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dqse_phase = 6'b000101;
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end
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5'b01001: // DQS = 504, DQ = 432, DQSE = 432
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begin
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dqs_phase = 7'b0110001;
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dq_phase = 7'b0100010;
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dqse_phase = 6'b001001;
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end
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5'b01010: // DQS = 540, DQ = 468
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begin
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dqs_phase = 7'b0010101;
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dq_phase = 7'b0000101;
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end
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5'b01011: // DQS = 576, DQ = 504
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begin
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dqs_phase = 7'b0011101;
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dq_phase = 7'b0001101;
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end
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5'b01100: // DQS = 612, DQ = 540
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begin
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dqs_phase = 7'b0100101;
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dq_phase = 7'b0010101;
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end
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5'b01101: // DQS = 648, DQ = 576
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begin
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dqs_phase = 7'b0101111;
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dq_phase = 7'b0011101;
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end
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5'b01110: // DQS = 684, DQ = 612
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begin
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dqs_phase = 7'b0110111;
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dq_phase = 7'b0100101;
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end
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5'b01111: // DQS = 720, DQ = 648
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begin
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dqs_phase = 7'b0010011;
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dq_phase = 7'b0000011;
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end
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5'b10000: // DQS = 756, DQ = 684
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begin
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dqs_phase = 7'b0011011;
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dq_phase = 7'b0001011;
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end
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5'b10001: // DQS = 792, DQ = 720
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begin
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dqs_phase = 7'b0100011;
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dq_phase = 7'b0010011;
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end
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default : begin end
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endcase
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end
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12: begin
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// DQSin = 60, DQS = 180, DQ = 120, DQSE = 90
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dqsi_phase = 3'b001;
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dqs_phase = 7'b0010100;
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dq_phase = 7'b0000100;
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dqse_phase = 6'b001100;
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case (avl_writedata[4:0])
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5'b00000: // DQS = 180, DQ = 120, DQSE = 90
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begin
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dqs_phase = 7'b0010100;
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dq_phase = 7'b0000100;
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dqse_phase = 6'b001100;
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end
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5'b00001: // DQS = 210, DQ = 150, DQSE = 120
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begin
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dqs_phase = 7'b0011100;
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dq_phase = 7'b0001100;
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dqse_phase = 6'b010000;
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end
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5'b00010: // DQS = 240, DQ = 180, DQSE = 150
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begin
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dqs_phase = 7'b0100100;
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dq_phase = 7'b0010100;
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dqse_phase = 6'b010100;
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end
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5'b00011: // DQS = 270, DQ = 210, DQSE = 180
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begin
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dqs_phase = 7'b0101100;
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dq_phase = 7'b0011100;
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dqse_phase = 6'b011000;
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end
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5'b00100: // DQS = 300, DQ = 240, DQSE = 210
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begin
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dqs_phase = 7'b0110110;
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dq_phase = 7'b0100100;
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dqse_phase = 6'b000110;
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end
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5'b00101: // DQS = 330, DQ = 270, DQSE = 240
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begin
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dqs_phase = 7'b0111110;
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dq_phase = 7'b0101100;
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dqse_phase = 6'b001010;
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end
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5'b00110: // DQS = 360, DQ = 300, DQSE = 270
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begin
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dqs_phase = 7'b0010010;
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dq_phase = 7'b0000010;
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dqse_phase = 6'b001110;
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end
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5'b00111: // DQS = 390, DQ = 330, DQSE = 300
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begin
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dqs_phase = 7'b0011010;
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dq_phase = 7'b0001010;
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dqse_phase = 6'b010011;
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end
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5'b01000: // DQS = 420, DQ = 360, DQSE = 330
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begin
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dqs_phase = 7'b0100010;
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dq_phase = 7'b0010010;
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dqse_phase = 6'b010111;
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end
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5'b01001: // DQS = 450, DQ = 390, DQSE = 360
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begin
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dqs_phase = 7'b0101010;
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dq_phase = 7'b0011010;
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dqse_phase = 6'b011011;
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end
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5'b01010: // DQS = 480, DQ = 420, DQSE = 390
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begin
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dqs_phase = 7'b0110001;
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dq_phase = 7'b0100010;
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dqse_phase = 6'b000101;
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end
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5'b01011: // DQS = 510, DQ = 450, DQSE = 420
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begin
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dqs_phase = 7'b0111001;
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dq_phase = 7'b0101010;
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dqse_phase = 6'b001001;
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end
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5'b01100: // DQS = 540, DQ = 480
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begin
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dqs_phase = 7'b0010101;
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dq_phase = 7'b0000101;
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end
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5'b01101: // DQS = 570, DQ = 510
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begin
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dqs_phase = 7'b0011101;
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dq_phase = 7'b0001101;
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end
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5'b01110: // DQS = 600, DQ = 540
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begin
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dqs_phase = 7'b0100101;
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dq_phase = 7'b0010101;
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end
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5'b01111: // DQS = 630, DQ = 570
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begin
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dqs_phase = 7'b0101101;
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dq_phase = 7'b0011101;
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end
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5'b10000: // DQS = 660, DQ = 600
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begin
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dqs_phase = 7'b0110111;
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dq_phase = 7'b0100101;
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end
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5'b10001: // DQS = 690, DQ = 630
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begin
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dqs_phase = 7'b0111111;
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dq_phase = 7'b0101101;
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end
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5'b10010: // DQS = 720, DQ = 660
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begin
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dqs_phase = 7'b0010011;
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dq_phase = 7'b0000011;
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end
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5'b10011: // DQS = 750, DQ = 690
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begin
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dqs_phase = 7'b0011011;
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dq_phase = 7'b0001011;
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end
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5'b10100: // DQS = 780, DQ = 720
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begin
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dqs_phase = 7'b0100011;
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dq_phase = 7'b0010011;
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end
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5'b10101: // DQS = 810, DQ = 750
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begin
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dqs_phase = 7'b0101011;
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dq_phase = 7'b0011011;
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end
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default : begin end
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endcase
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end
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default : begin end
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endcase
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end
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endmodule
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