206 lines
7.2 KiB
VHDL
206 lines
7.2 KiB
VHDL
-- megafunction wizard: %FIFO%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: dcfifo
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-- ============================================================
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-- File Name: spiFifo.vhd
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-- Megafunction Name(s):
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-- dcfifo
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--
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-- Simulation Library Files(s):
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-- altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
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-- ************************************************************
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--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, the Altera Quartus Prime License Agreement,
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--the Altera MegaCore Function License Agreement, or other
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--applicable license agreement, including, without limitation,
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--that your use is for the sole purpose of programming logic
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--devices manufactured by Altera and sold by Altera or its
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--authorized distributors. Please refer to the applicable
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--agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY spiFifo IS
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PORT
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(
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aclr : IN STD_LOGIC := '0';
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data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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rdclk : IN STD_LOGIC ;
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rdreq : IN STD_LOGIC ;
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wrclk : IN STD_LOGIC ;
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wrreq : IN STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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rdempty : OUT STD_LOGIC ;
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wrfull : OUT STD_LOGIC
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);
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END spiFifo;
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ARCHITECTURE SYN OF spififo IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC ;
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SIGNAL sub_wire2 : STD_LOGIC ;
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COMPONENT dcfifo
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GENERIC (
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intended_device_family : STRING;
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lpm_numwords : NATURAL;
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lpm_showahead : STRING;
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lpm_type : STRING;
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lpm_width : NATURAL;
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lpm_widthu : NATURAL;
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overflow_checking : STRING;
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rdsync_delaypipe : NATURAL;
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read_aclr_synch : STRING;
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underflow_checking : STRING;
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use_eab : STRING;
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write_aclr_synch : STRING;
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wrsync_delaypipe : NATURAL
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);
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PORT (
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aclr : IN STD_LOGIC ;
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data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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rdclk : IN STD_LOGIC ;
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rdreq : IN STD_LOGIC ;
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wrclk : IN STD_LOGIC ;
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wrreq : IN STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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rdempty : OUT STD_LOGIC ;
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wrfull : OUT STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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q <= sub_wire0(7 DOWNTO 0);
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rdempty <= sub_wire1;
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wrfull <= sub_wire2;
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dcfifo_component : dcfifo
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GENERIC MAP (
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intended_device_family => "Cyclone V",
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lpm_numwords => 8,
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lpm_showahead => "OFF",
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lpm_type => "dcfifo",
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lpm_width => 8,
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lpm_widthu => 3,
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overflow_checking => "ON",
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rdsync_delaypipe => 4,
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read_aclr_synch => "OFF",
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underflow_checking => "ON",
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use_eab => "ON",
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write_aclr_synch => "OFF",
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wrsync_delaypipe => 4
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)
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PORT MAP (
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aclr => aclr,
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data => data,
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rdclk => rdclk,
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rdreq => rdreq,
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wrclk => wrclk,
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wrreq => wrreq,
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q => sub_wire0,
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rdempty => sub_wire1,
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wrfull => sub_wire2
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);
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
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-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
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-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
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-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
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-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
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-- Retrieval info: PRIVATE: Clock NUMERIC "4"
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-- Retrieval info: PRIVATE: Depth NUMERIC "8"
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-- Retrieval info: PRIVATE: Empty NUMERIC "1"
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-- Retrieval info: PRIVATE: Full NUMERIC "1"
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
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-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
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-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
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-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
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-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
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-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
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-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
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-- Retrieval info: PRIVATE: Width NUMERIC "8"
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-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
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-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
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-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
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-- Retrieval info: PRIVATE: output_width NUMERIC "8"
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-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
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-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
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-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
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-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
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-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
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-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
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-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
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-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8"
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-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
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-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
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-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "3"
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-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
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-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
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-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
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-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
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-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
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-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
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-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
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-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
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-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
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-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
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-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
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-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
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-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
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-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
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-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
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-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
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-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
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-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
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-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
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-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
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-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
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-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
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-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL spiFifo.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL spiFifo.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL spiFifo.cmp FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL spiFifo.bsf FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL spiFifo_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: altera_mf
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