110 lines
2.5 KiB
VHDL
110 lines
2.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.wishbone_package.all;
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use work.crossbar_package.all;
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use work.ebr_package.all;
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use work.lm32_package.all;
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use work.simple_pll_package.all;
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entity example is
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port(
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clk_base : in std_logic;
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rstn_base : in std_logic
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);
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end example;
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architecture rtl of example is
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constant masters : natural := 2;
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constant slaves : natural := 2;
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signal clk : std_logic;
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signal rst : std_logic;
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signal locked : std_logic;
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signal intercon_slave_i : wishbone_slave_in_vector(masters-1 downto 0);
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signal intercon_slave_o : wishbone_slave_out_vector(masters-1 downto 0);
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signal intercon_master_i : wishbone_master_in_vector(slaves-1 downto 0);
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signal intercon_master_o : wishbone_master_out_vector(slaves-1 downto 0);
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begin
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rst <= not rstn_base or not locked;
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clk_pll : simple_pll
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generic map
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(
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c0_mul => 2,
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c0_div => 1,
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c1_mul => 4,
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c1_div => 1,
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in_freq => 50000
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)
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port map
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(
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inclk0 => clk_base,
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c0 => clk,
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c1 => open,
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locked => locked
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);
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ebr_memory : ebr
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generic map
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(
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size => 4096
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)
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port map
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(
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clk => clk,
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rst => rst,
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slave_i => intercon_master_o(0),
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slave_o => intercon_master_i(0)
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);
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monitor_memory : ebr
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generic map
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(
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size => 2048
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)
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port map
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(
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clk => clk,
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rst => rst,
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slave_i => intercon_master_o(1),
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slave_o => intercon_master_i(1)
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);
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cpu0 : lm32_vhdl
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port map
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(
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clk => clk,
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rst => rst,
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interrupt => x"00000000",
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data_o => intercon_slave_i(0),
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data_i => intercon_slave_o(0),
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inst_o => intercon_slave_i(1),
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inst_i => intercon_slave_o(1)
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);
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intercon : crossbar
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generic map
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(
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masters => masters,
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slaves => slaves,
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-- Device 0 has range 00000000-00000fff
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-- Device 1 has range 10000000-100007ff
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address => (0 => x"00000000",
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1 => x"10000000"),
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mask => (0 => x"fffff000",
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1 => x"fffff800")
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)
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port map
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(
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clk => clk,
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rst => rst,
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slave_i => intercon_slave_i,
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slave_o => intercon_slave_o,
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master_i => intercon_master_i,
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master_o => intercon_master_o
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);
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end;
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