151 lines
4.5 KiB
VHDL
151 lines
4.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rwp_ram_package.all;
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entity fifo is
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generic(
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sync_depth : natural := 3;
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gray_code : boolean := true;
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addr_width : natural := 4;
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data_width : natural := 32);
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port(
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rst : in std_logic;
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-- write port, only set w_en when w_rdy
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w_clk : in std_logic;
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w_rdy : out std_logic;
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w_en : in std_logic;
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w_data : in std_logic_vector(data_width-1 downto 0);
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-- (pre)alloc port, can be unused
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a_clk : in std_logic;
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a_rdy : out std_logic;
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a_en : in std_logic;
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-- read port, only set r_en when r_rdy
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-- data is valid the cycle after r_en raised
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r_clk : in std_logic;
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r_rdy : out std_logic;
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r_en : in std_logic;
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r_data : out std_logic_vector(data_width-1 downto 0));
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end fifo;
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architecture rtl of fifo is
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subtype counter is unsigned(addr_width downto 0);
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type counter_shift is array(sync_depth downto 0) of counter;
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signal r_idx_bnry : counter;
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signal r_idx_gray : counter;
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signal w_idx_bnry : counter;
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signal w_idx_gray : counter;
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signal a_idx_bnry : counter;
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signal a_idx_gray : counter;
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signal r_idx_shift_w : counter_shift; -- r_idx_gray in w_clk
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signal r_idx_shift_a : counter_shift; -- r_idx_gray in a_clk
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signal w_idx_shift_r : counter_shift; -- w_idx_gray in r_clk
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function bin2gray(a : unsigned) return unsigned is
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variable o : unsigned(a'length downto 0);
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begin
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if gray_code then
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o := (a & '0') xor ('0' & a);
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else
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o := (a & '0');
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end if;
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return o(a'length downto 1);
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end bin2gray;
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function index(a : counter) return std_logic_vector is
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begin
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return std_logic_vector(a(addr_width-1 downto 0));
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end index;
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function empty(a, b : counter) return std_logic is
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begin
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if a = b then
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return '1';
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else
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return '0';
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end if;
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end empty;
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function full(a, b : counter) return std_logic is
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variable mask : counter := (others => '0');
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begin
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-- In binary a full FIFO has indexes (a XOR 1000...00) = b
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-- bin2gray is a linear function, thus:
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-- a XOR 1000..00 = b iff
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-- bin2gray(a XOR 1000...00) = bin2gray(b) iff
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-- bin2gray(a) XOR bin2gray(1000...00) = bin2gray(b) iif
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-- bin2gray(a) XOR 1100..00 = bin2gray(b)
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mask(addr_width) := '1';
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mask := bin2gray(mask);
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if (a xor mask) = b then
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return '1';
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else
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return '0';
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end if;
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end full;
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begin
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ram : rwp_ram
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generic map(addr_width => addr_width, data_width => data_width)
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port map(w_clk => w_clk, w_en => w_en, w_addr => index(w_idx_bnry), w_data => w_data,
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r_clk => r_clk, r_en => r_en, r_addr => index(r_idx_bnry), r_data => r_data);
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read : process(r_clk)
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variable idx : counter;
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begin
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if rising_edge(r_clk) then
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if rst = '1' then
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idx := (others => '0');
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elsif r_en = '1' then
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idx := r_idx_bnry + 1;
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else
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idx := r_idx_bnry;
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end if;
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r_idx_bnry <= idx;
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r_idx_gray <= bin2gray(idx);
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w_idx_shift_r(sync_depth downto 1) <= w_idx_shift_r(sync_depth-1 downto 0);
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end if;
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end process;
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w_idx_shift_r(0) <= w_idx_gray;
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r_rdy <= not empty(r_idx_gray, w_idx_shift_r(sync_depth));
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write : process(w_clk)
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variable idx : counter;
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begin
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if rising_edge(w_clk) then
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if rst = '1' then
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idx := (others => '0');
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elsif w_en = '1' then
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idx := w_idx_bnry + 1;
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else
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idx := w_idx_bnry;
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end if;
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w_idx_bnry <= idx;
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w_idx_gray <= bin2gray(idx);
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r_idx_shift_w(sync_depth downto 1) <= r_idx_shift_w(sync_depth-1 downto 0);
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end if;
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end process;
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r_idx_shift_w(0) <= r_idx_gray;
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w_rdy <= not full(w_idx_gray, r_idx_shift_w(sync_depth));
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alloc : process(a_clk)
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variable idx : counter;
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begin
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if rising_edge(a_clk) then
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if rst = '1' then
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idx := (others => '0');
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elsif a_en = '1' then
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idx := a_idx_bnry + 1;
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else
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idx := a_idx_bnry;
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end if;
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a_idx_bnry <= idx;
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a_idx_gray <= bin2gray(idx);
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r_idx_shift_a(sync_depth downto 1) <= r_idx_shift_a(sync_depth-1 downto 0);
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end if;
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end process;
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r_idx_shift_a(0) <= r_idx_gray;
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a_rdy <= not full(a_idx_gray, r_idx_shift_a(sync_depth));
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end rtl;
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