49 lines
1.3 KiB
VHDL
49 lines
1.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.wishbone_package.all;
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entity test_slave is
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generic(
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delay : integer := 1
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);
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port(
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-- Common wishbone signals
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clk : in std_logic;
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rst : in std_logic;
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-- Slave control port
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slave_i : in wishbone_slave_in;
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slave_o : out wishbone_slave_out
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);
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end test_slave;
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architecture rtl of test_slave is
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type result_t is array(delay downto 0) of wishbone_data;
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signal ack_shift : std_logic_vector(delay downto 0);
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signal res_shift : result_t;
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begin
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slave_o.ACK <= ack_shift(0);
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slave_o.ERR <= '0';
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slave_o.RTY <= '0';
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slave_o.DAT <= res_shift(0);
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slave_o.STALL <= '0';
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ack_shift(delay) <= slave_i.STB and slave_i.CYC;
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main : process(clk)
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begin
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if rising_edge(clk) then
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if (rst = '1') then
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ack_shift(delay-1 downto 0) <= (others => '0');
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res_shift <= (others => (others => '0'));
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else
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if (slave_i.CYC = '1' and slave_i.STB = '1' and slave_i.WE = '0') then
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res_shift(delay) <= std_logic_vector(unsigned(res_shift(delay)) + 1);
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end if;
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ack_shift(delay-1 downto 0) <= ack_shift(delay downto 1);
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res_shift(delay-1 downto 0) <= res_shift(delay downto 1);
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end if;
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end if;
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end process;
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end rtl;
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