311 lines
10 KiB
Systemverilog
311 lines
10 KiB
Systemverilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_burst_adapter/new_source/altera_incr_burst_converter.sv#1 $
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// $Revision: #1 $
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// $Date: 2015/08/09 $
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// $Author: swbranch $
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// ----------------------------------------------------------
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// This component is used for INCR Avalon slave
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// (slave which only supports INCR) or AXI slave.
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// It converts burst length of input packet
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// to match slave burst.
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// ----------------------------------------------------------
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`timescale 1 ns / 1 ns
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module altera_incr_burst_converter
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#(
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parameter
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// ----------------------------------------
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// Burst length Parameters
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// (real burst length value, not bytecount)
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// ----------------------------------------
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MAX_IN_LEN = 16,
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MAX_OUT_LEN = 4,
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NUM_SYMBOLS = 4,
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ADDR_WIDTH = 12,
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BNDRY_WIDTH = 12,
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BURSTSIZE_WIDTH = 3,
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IN_NARROW_SIZE = 0,
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PURELY_INCR_AVL_SYS = 0,
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// ------------------
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// Derived Parameters
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// ------------------
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LEN_WIDTH = log2ceil(MAX_IN_LEN) + 1,
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OUT_LEN_WIDTH = log2ceil(MAX_OUT_LEN) + 1,
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LOG2_NUMSYMBOLS = log2ceil(NUM_SYMBOLS)
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)
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(
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input clk,
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input reset,
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input enable,
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input is_write,
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input [LEN_WIDTH - 1 : 0] in_len,
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input in_sop,
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input [ADDR_WIDTH - 1 : 0] in_addr,
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input [ADDR_WIDTH - 1 : 0] in_addr_reg,
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input [BNDRY_WIDTH - 1 : 0] in_burstwrap_reg,
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input [BURSTSIZE_WIDTH - 1 : 0] in_size_t,
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input [BURSTSIZE_WIDTH - 1 : 0] in_size_reg,
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// converted output length
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// out_len : compressed burst, read
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// uncompressed_len: uncompressed, write
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output reg [LEN_WIDTH - 1 : 0] out_len,
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output reg [LEN_WIDTH - 1 : 0] uncompr_out_len,
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// Compressed address output
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output reg [ADDR_WIDTH - 1 : 0] out_addr,
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output reg new_burst_export
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);
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// ----------------------------------------
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// Signals for wrapping support
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// ----------------------------------------
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reg [LEN_WIDTH - 1 : 0] remaining_len;
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reg [LEN_WIDTH - 1 : 0] next_out_len;
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reg [LEN_WIDTH - 1 : 0] next_rem_len;
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reg [LEN_WIDTH - 1 : 0] uncompr_remaining_len;
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reg [LEN_WIDTH - 1 : 0] next_uncompr_remaining_len;
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reg [LEN_WIDTH - 1 : 0] next_uncompr_rem_len;
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reg new_burst;
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reg uncompr_sub_burst;
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// Avoid QIS warning
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wire [OUT_LEN_WIDTH - 1 : 0] max_out_length;
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assign max_out_length = MAX_OUT_LEN[OUT_LEN_WIDTH - 1 : 0];
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always_comb begin
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new_burst_export = new_burst;
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end
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// -------------------------------------------
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// length remaining calculation
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// -------------------------------------------
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always_comb begin : proc_uncompressed_remaining_len
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if ((in_len <= max_out_length) && is_write) begin
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uncompr_remaining_len = in_len;
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end else begin
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uncompr_remaining_len = max_out_length;
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end
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if (uncompr_sub_burst)
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uncompr_remaining_len = next_uncompr_rem_len;
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end
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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next_uncompr_rem_len <= 0;
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end
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else if (enable) begin
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next_uncompr_rem_len <= uncompr_remaining_len - 1'b1; // in term of length, it just reduces 1
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end
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end
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always_comb begin : proc_compressed_remaining_len
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remaining_len = in_len;
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if (!new_burst)
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remaining_len = next_rem_len;
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end
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always_ff@(posedge clk or posedge reset) begin : proc_next_uncompressed_remaining_len
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if(reset) begin
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next_uncompr_remaining_len <= '0;
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end
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else if (enable) begin
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if (in_sop) begin
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next_uncompr_remaining_len <= in_len - max_out_length;
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end
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else if (!uncompr_sub_burst)
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next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
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end
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end
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always_comb begin
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next_out_len = max_out_length;
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if (remaining_len < max_out_length) begin
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next_out_len = remaining_len;
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end
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end // always_comb
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// --------------------------------------------------
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// Length remaining calculation : compressed
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// --------------------------------------------------
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// length remaining for compressed transaction
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// for wrap, need special handling for first out length
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always_ff @(posedge clk, posedge reset) begin
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if (reset)
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next_rem_len <= 0;
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else if (enable) begin
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if (new_burst)
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next_rem_len <= in_len - max_out_length;
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else
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next_rem_len <= next_rem_len - max_out_length;
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end
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end
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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uncompr_sub_burst <= 0;
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end
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else if (enable && is_write) begin
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uncompr_sub_burst <= (uncompr_remaining_len > 1'b1);
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end
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end
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// --------------------------------------------------
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// Control signals
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// --------------------------------------------------
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wire end_compressed_sub_burst;
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assign end_compressed_sub_burst = (remaining_len == next_out_len);
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// new_burst:
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// the converter takes in_len for new calculation
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always_ff @(posedge clk, posedge reset) begin
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if (reset)
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new_burst <= 1;
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else if (enable)
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new_burst <= end_compressed_sub_burst;
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end
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// --------------------------------------------------
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// Output length
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// --------------------------------------------------
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// register out_len for compressed trans
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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out_len <= 0;
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end
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else if (enable) begin
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out_len <= next_out_len;
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end
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end
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// register uncompr_out_len for uncompressed trans
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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uncompr_out_len <= '0;
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end
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else if (enable) begin
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uncompr_out_len <= uncompr_remaining_len;
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end
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end
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// --------------------------------------------------
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// Address Calculation
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// --------------------------------------------------
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reg [ADDR_WIDTH - 1 : 0] addr_incr_sel;
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reg [ADDR_WIDTH - 1 : 0] addr_incr_sel_reg;
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reg [ADDR_WIDTH - 1 : 0] addr_incr_full_size;
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localparam [ADDR_WIDTH - 1 : 0] ADDR_INCR = MAX_OUT_LEN << LOG2_NUMSYMBOLS;
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generate
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if (IN_NARROW_SIZE) begin : narrow_addr_incr
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reg [ADDR_WIDTH - 1 : 0] addr_incr_variable_size;
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reg [ADDR_WIDTH - 1 : 0] addr_incr_variable_size_reg;
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assign addr_incr_variable_size = MAX_OUT_LEN << in_size_t;
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assign addr_incr_variable_size_reg = MAX_OUT_LEN << in_size_reg;
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assign addr_incr_sel = addr_incr_variable_size;
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assign addr_incr_sel_reg = addr_incr_variable_size_reg;
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end
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else begin : full_addr_incr
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assign addr_incr_full_size = ADDR_INCR[ADDR_WIDTH - 1 : 0];
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assign addr_incr_sel = addr_incr_full_size;
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assign addr_incr_sel_reg = addr_incr_full_size;
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end
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endgenerate
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reg [ADDR_WIDTH - 1 : 0] next_out_addr;
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reg [ADDR_WIDTH - 1 : 0] incremented_addr;
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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out_addr <= '0;
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end else begin
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if (enable) begin
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out_addr <= (next_out_addr);
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end
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end
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end
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generate
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if (!PURELY_INCR_AVL_SYS) begin : incremented_addr_normal
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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incremented_addr <= '0;
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end
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else if (enable) begin
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incremented_addr <= (next_out_addr + addr_incr_sel_reg);
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if (new_burst) begin
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incremented_addr <= (next_out_addr + addr_incr_sel);
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end
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end
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end // always_ff @
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always_comb begin
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next_out_addr = in_addr;
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if (!new_burst) begin
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next_out_addr = incremented_addr;
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end
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end
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end
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else begin : incremented_addr_pure_av
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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incremented_addr <= '0;
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end
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else if (enable) begin
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incremented_addr <= (next_out_addr + addr_incr_sel_reg);
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end
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end // always_ff @
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always_comb begin
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next_out_addr = in_addr;
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if (!new_burst) begin
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next_out_addr = (incremented_addr);
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end
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end
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end
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endgenerate
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// --------------------------------------------------
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// Calculates the log2ceil of the input value
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// --------------------------------------------------
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function integer log2ceil;
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input integer val;
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reg[31:0] i;
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begin
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i = 1;
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log2ceil = 0;
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while (i < val) begin
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log2ceil = log2ceil + 1;
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i = i[30:0] << 1;
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end
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end
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endfunction
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endmodule
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