88 lines
3.4 KiB
Verilog
88 lines
3.4 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
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// $Revision: #1 $
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// $Date: 2015/08/09 $
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// $Author: swbranch $
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// -----------------------------------------------
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// Reset Synchronizer
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// -----------------------------------------------
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`timescale 1 ns / 1 ns
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module altera_reset_synchronizer
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#(
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parameter ASYNC_RESET = 1,
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parameter DEPTH = 2
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)
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(
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input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
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input clk,
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output reset_out
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);
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// -----------------------------------------------
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// Synchronizer register chain. We cannot reuse the
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// standard synchronizer in this implementation
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// because our timing constraints are different.
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//
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// Instead of cutting the timing path to the d-input
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// on the first flop we need to cut the aclr input.
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//
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// We omit the "preserve" attribute on the final
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// output register, so that the synthesis tool can
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// duplicate it where needed.
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// -----------------------------------------------
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(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
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reg altera_reset_synchronizer_int_chain_out;
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generate if (ASYNC_RESET) begin
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// -----------------------------------------------
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// Assert asynchronously, deassert synchronously.
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// -----------------------------------------------
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always @(posedge clk or posedge reset_in) begin
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if (reset_in) begin
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altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
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altera_reset_synchronizer_int_chain_out <= 1'b1;
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end
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else begin
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altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
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altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
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altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
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end
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end
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assign reset_out = altera_reset_synchronizer_int_chain_out;
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end else begin
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// -----------------------------------------------
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// Assert synchronously, deassert synchronously.
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// -----------------------------------------------
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always @(posedge clk) begin
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altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
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altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
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altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
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end
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assign reset_out = altera_reset_synchronizer_int_chain_out;
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end
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endgenerate
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endmodule
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