121 lines
3.3 KiB
Verilog
121 lines
3.3 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module ddr3_p0_acv_ldc
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(
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pll_hr_clk,
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pll_dq_clk,
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pll_dqs_clk,
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dll_phy_delayctrl,
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afi_clk,
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avl_clk,
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adc_clk,
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adc_clk_cps,
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hr_clk
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);
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parameter DLL_DELAY_CTRL_WIDTH = "";
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parameter ADC_PHASE_SETTING = 0;
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parameter ADC_INVERT_PHASE = "false";
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parameter IS_HHP_HPS = "false";
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input pll_hr_clk;
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input pll_dq_clk;
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input pll_dqs_clk;
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input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
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output afi_clk;
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output avl_clk;
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output adc_clk;
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output adc_clk_cps;
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output hr_clk;
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wire phy_clk_dqs;
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wire phy_clk_dq;
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wire phy_clk_hr;
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wire phy_clk_dqs_2x;
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wire phy_clk_addr_cmd;
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wire phy_clk_addr_cmd_cps;
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generate
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if (IS_HHP_HPS == "true") begin
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assign phy_clk_hr = pll_hr_clk;
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assign phy_clk_dq = pll_dq_clk;
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assign phy_clk_dqs = pll_dqs_clk;
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assign phy_clk_dqs_2x = 1'b0;
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end else begin
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cyclonev_phy_clkbuf phy_clkbuf (
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.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
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.outclk ({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
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);
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end
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endgenerate
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wire [3:0] leveled_dqs_clocks;
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wire [3:0] leveled_hr_clocks;
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wire hr_seq_clock;
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cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
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.clkin (phy_clk_dqs),
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.delayctrlin (dll_phy_delayctrl),
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.clkout(leveled_dqs_clocks)
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);
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defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
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assign afi_clk = leveled_dqs_clocks[0];
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cyclonev_leveling_delay_chain leveling_delay_chain_hr (
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.clkin (phy_clk_hr),
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.delayctrlin (),
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.clkout(leveled_hr_clocks)
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);
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defparam leveling_delay_chain_hr.physical_clock_source = "HR";
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assign avl_clk = leveled_hr_clocks[0];
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cyclonev_clk_phase_select clk_phase_select_addr_cmd (
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.clkin(leveled_dqs_clocks),
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.clkout(adc_clk_cps)
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);
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defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
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defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
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defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
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defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
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cyclonev_clk_phase_select clk_phase_select_hr (
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.phasectrlin(),
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.phaseinvertctrl(),
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.dqsin(),
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`ifndef SIMGEN
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.clkin (leveled_hr_clocks[0]),
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`else
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.clkin (leveled_hr_clocks),
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`endif
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.clkout (hr_seq_clock)
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);
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defparam clk_phase_select_hr.physical_clock_source = "HR";
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defparam clk_phase_select_hr.use_phasectrlin = "false";
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defparam clk_phase_select_hr.phase_setting = 0;
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assign hr_clk = hr_seq_clock;
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generate
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if (ADC_INVERT_PHASE == "true")
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begin
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assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
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end else begin
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assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
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end
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endgenerate
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endmodule
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