59 lines
1.6 KiB
Systemverilog
59 lines
1.6 KiB
Systemverilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
|
|
// Your use of Altera Corporation's design tools, logic functions and other
|
|
// software and tools, and its AMPP partner logic functions, and any output
|
|
// files any of the foregoing (including device programming or simulation
|
|
// files), and any associated documentation or information are expressly subject
|
|
// to the terms and conditions of the Altera Program License Subscription
|
|
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
|
// license agreement, including, without limitation, that your use is for the
|
|
// sole purpose of programming logic devices manufactured by Altera and sold by
|
|
// Altera or its authorized distributors. Please refer to the applicable
|
|
// agreement for further details.
|
|
|
|
|
|
// $Id: //acds/rel/15.1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $
|
|
// $Revision: #1 $
|
|
// $Date: 2015/08/09 $
|
|
// $Author: swbranch $
|
|
|
|
// -------------------------------------------------------
|
|
// Altera IRQ Mapper
|
|
//
|
|
// Parameters
|
|
// NUM_RCVRS : 0
|
|
// SENDER_IRW_WIDTH : 32
|
|
// IRQ_MAP :
|
|
//
|
|
// -------------------------------------------------------
|
|
|
|
`timescale 1 ns / 1 ns
|
|
|
|
module ddr3_s0_irq_mapper
|
|
(
|
|
// -------------------
|
|
// Clock & Reset
|
|
// -------------------
|
|
input clk,
|
|
input reset,
|
|
|
|
// -------------------
|
|
// IRQ Receivers
|
|
// -------------------
|
|
|
|
// -------------------
|
|
// Command Source (Output)
|
|
// -------------------
|
|
output reg [31 : 0] sender_irq
|
|
);
|
|
|
|
initial sender_irq = 0;
|
|
|
|
always @* begin
|
|
sender_irq = 0;
|
|
|
|
end
|
|
|
|
endmodule
|
|
|
|
|