24 lines
739 B
VHDL
24 lines
739 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package rwp_ram_package is
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-- Read during write has an undefined result
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component rwp_ram is
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generic(
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addr_width : natural := 4;
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data_width : natural := 32);
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port(
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-- write port
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w_clk : in std_logic;
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w_en : in std_logic;
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w_addr : in std_logic_vector(addr_width-1 downto 0);
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w_data : in std_logic_vector(data_width-1 downto 0);
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-- read port
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r_clk : in std_logic;
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r_en : in std_logic;
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r_addr : in std_logic_vector(addr_width-1 downto 0);
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r_data : out std_logic_vector(data_width-1 downto 0));
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end component;
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end rwp_ram_package;
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