61 lines
1.4 KiB
VHDL
61 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library ip;
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use ip.wishbone_package.all;
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use ip.all;
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entity sram_wb is
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port(
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clk : in std_logic;
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rst : in std_logic;
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-- Wishbone
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wb_in : in wishbone_v3_slave_in;
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wb_out : out wishbone_v3_slave_out
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);
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end entity sram_wb;
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architecture RTL of sram_wb is
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signal ram_address : std_logic_vector(10 DOWNTO 0);
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signal ram_byteena : std_logic_vector(3 DOWNTO 0);
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signal ram_dIn : std_logic_vector(31 DOWNTO 0);
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signal ram_we : std_logic;
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signal ram_dOut : std_logic_vector(31 DOWNTO 0);
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signal ackRead : std_logic;
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begin
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ram0_inst : entity ip.ram0
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port map(
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address => ram_address,
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byteena => ram_byteena,
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clock => clk,
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data => ram_dIn,
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wren => ram_we,
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q => ram_dOut
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);
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sram_p : process(clk, rst) is
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begin
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if rst = '1' then
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ackRead <= '0';
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elsif rising_edge(clk) then
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ackRead <= '0';
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if wb_in.CYC = '1' and wb_in.STB = '1' and wb_in.WE = '0' then
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ackRead <= '1';
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end if;
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end if;
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end process sram_p;
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ram_address <= wb_in.ADR(12 downto 2);
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ram_we <= wb_in.WE and wb_in.CYC and wb_in.STB;
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wb_out.ACK <= (wb_in.WE or ackRead) and wb_in.CYC and wb_in.STB;
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wb_out.ERR <= '0';
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wb_out.RTY <= '0';
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wb_out.DAT <= ram_dOut;
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ram_dIn <= wb_in.DAT;
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ram_byteena <= wb_in.SEL;
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end architecture RTL;
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