180 lines
6.2 KiB
VHDL
180 lines
6.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.flashrom_pkg.all;
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entity flashrom_controller is
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port(
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clk : in std_logic;
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rst : in std_logic;
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clr : in std_logic;
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-- Control IF
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ready : out std_logic; -- The controller is ready to accept commands
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page : in std_logic_vector(FLASHROM_ADDR_WIDTH - 1 downto 0);
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sync_stb : in std_logic; -- Synchronize current memory page with chip, only sampled when ready
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load_stb : in std_logic; -- Load page into local buffer, only sampled when ready
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status_update_stb : in std_logic; -- Update status vector
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status : out std_logic_vector(7 downto 0); -- value of the status register (update using status_update_stb)
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info : out std_logic_vector(31 downto 0); -- value of the information register (updated on reset)
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-- Data IF
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data_in : in std_logic_vector(7 downto 0);
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data_in_valid : in std_logic;
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data_out : out std_logic_vector(7 downto 0);
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data_out_valid : out std_logic;
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-- SPI flash hardware signals
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spi_si : out std_logic; -- SPI serial in
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spi_so : in std_logic; -- SPI serial out
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spi_sck : out std_logic; -- Create clock using PLL, then supply to chip and this module
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spi_reset_n : out std_logic; -- SPI hard reset
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spi_cs_n : out std_logic; -- SPI chip select
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spi_wp_n : out std_logic -- SPI write protect
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);
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end entity flashrom_controller;
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architecture RTL of flashrom_controller is
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constant spif_max_word_length : integer := 32;
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constant max_dummy_bits : integer := 63;
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constant bootup_delay : integer := 4000;
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type state_t is (INIT, GETINFO, GETSTATUS, LOADPAGE, IDLE);
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signal state : state_t;
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signal spif_data_in_valid : std_logic;
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signal spif_data_in : std_logic_vector(spif_max_word_length - 1 downto 0);
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signal spif_data_in_length : integer range 0 to spif_max_word_length;
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signal spif_data_next : std_logic;
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signal spif_data_out : std_logic_vector(spif_max_word_length - 1 downto 0);
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signal spif_data_out_valid : std_logic;
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signal spif_data_out_length : integer range 0 to spif_max_word_length;
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signal words_sent : integer range 0 to 511;
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signal spif_data_out_dummy_bits : integer range 0 to max_dummy_bits;
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signal spif_transmission_active : std_logic;
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begin
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spi_wp_n <= '1';
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flashrom_spi_inst : entity work.flashrom_spi
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generic map(
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clk_divider => 4,
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max_word_length => spif_max_word_length,
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max_dummy_bits => max_dummy_bits)
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port map(
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clk => clk,
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rst => rst,
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clr => clr,
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spi_si => spi_si,
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spi_so => spi_so,
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spi_sck => spi_sck,
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spi_cs_n => spi_cs_n,
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data_in_valid => spif_data_in_valid,
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data_in => spif_data_in,
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data_in_length => spif_data_in_length,
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data_next => spif_data_next,
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data_out => spif_data_out,
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data_out_valid => spif_data_out_valid,
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data_out_length => spif_data_out_length,
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data_out_dummy_bits => spif_data_out_dummy_bits,
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transmission_active => spif_transmission_active);
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flashrom_controller_p : process(clk, rst) is
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variable temp_cnt : integer range 0 to bootup_delay;
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variable done : boolean;
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procedure default_state is
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begin
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spi_reset_n <= '1';
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spif_data_in_valid <= '0';
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done := false;
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end procedure default_state;
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procedure reset_state is
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begin
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default_state;
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state <= INIT;
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spi_reset_n <= '0';
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words_sent <= 0;
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spif_data_in <= (others => '0');
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spif_data_in_length <= 0;
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spif_data_out_length <= 0;
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spif_data_out_dummy_bits <= 0;
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temp_cnt := 0;
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end procedure reset_state;
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procedure run_command_single(constant data_in_length : integer; constant data_out_length : integer; constant data_out_dummy_bits : integer; constant nTxWords : integer; constant data_in : std_logic_vector) is
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begin
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spif_data_in_length <= data_in_length;
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spif_data_out_length <= data_out_length;
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spif_data_out_dummy_bits <= data_out_dummy_bits;
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spif_data_in_valid <= '1';
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spif_data_in <= data_in & padBits(spif_data_in, data_in);
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if temp_cnt = nTxWords then
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spif_data_in_valid <= '0';
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elsif spif_data_next = '1' then
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temp_cnt := temp_cnt + 1;
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end if;
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if spif_data_out_valid = '1' and (temp_cnt = nTxWords) then
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spif_data_in_valid <= '0';
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done := true;
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state <= IDLE;
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temp_cnt := 0;
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end if;
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end procedure run_command_single;
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begin
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if rst = '1' then
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reset_state;
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elsif rising_edge(clk) then
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default_state;
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if clr = '1' then
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reset_state;
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else
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case state is
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when INIT =>
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words_sent <= 0;
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if temp_cnt = bootup_delay then
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temp_cnt := 0;
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state <= GETINFO;
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else
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temp_cnt := temp_cnt + 1;
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end if;
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when GETINFO => -- TODO: In simulation I can only call this command once?!
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run_command_single(8, 32, 8, 5, FLASHROM_COMMAND_MANUFACTURER_ID);
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if done then
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info <= spif_data_out;
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end if;
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when IDLE =>
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temp_cnt := 0;
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if status_update_stb = '1' then
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state <= GETSTATUS;
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end if;
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if load_stb = '1' then --debug only
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state <= LOADPAGE;
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end if;
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when GETSTATUS =>
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run_command_single(8, 8, 16, 3, FLASHROM_COMMAND_GET_STATUS);
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if done then
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status <= spif_data_out(7 downto 0);
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end if;
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when LOADPAGE =>
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run_command_single(24, 8, 34, 256/3+3, FLASHROM_COMMAND_CONT_ARRAY_READ & page); -- TODO: This will read one byte too far
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if done then
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report "Load page done." severity note;
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end if;
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end case;
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end if;
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end if;
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end process flashrom_controller_p;
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ready <= '1' when state = IDLE else '0';
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data_out <= spif_data_out(7 downto 0);
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data_out_valid <= spif_data_out_valid when state = LOADPAGE else '0';
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end architecture RTL;
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