rgboard/diamond/ws2812wall.ldf

36 lines
1.5 KiB
XML

<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="ws2812wall" device="LCMXO2-7000HC-5TG144C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
<Options def_top="uart_tx" top="top"/>
<Source name="../design/edgeDetector.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../design/ram.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../design/synchronizer.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../design/top_pkg.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../design/top.vhd" type="VHDL" type_short="VHDL">
<Options top_module="top"/>
</Source>
<Source name="../design/uart_rx.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../design/uart_tx.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../ws2812b-vhdl/ws2812b/ws2812b_phy.vhd" type="VHDL" type_short="VHDL">
<Options lib="ws2812b"/>
</Source>
<Source name="ws2812wall.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="ws2812wall1.sty"/>
</BaliProject>