trashernet/bench/bench_trashernet_phy.vhd

-- -------------------------------------------------------------------------- --
--               TRASHERNET - A Trashy Ethernet Stack for FPGAs               --
-- -------------------------------------------------------------------------- --
-- bench_trashernet_phy.vhd : Stimulus-only test bench for the PHY part
--   Tests only the RX path.
-- -------------------------------------------------------------------------- --
-- Author       : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License      : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.bench_pkg.all;

library trashernet;
use trashernet.trashernet_pkg.all;

entity bench_trashernet_phy is
end entity bench_trashernet_phy;

architecture bench of bench_trashernet_phy is
	signal clk            : std_logic;
	signal phy_clk        : std_logic;
	signal rst            : std_logic;
	signal phy_out : phy_out_t;
	signal phy_in : phy_in_t;
	signal rx_p : std_logic;
	signal tx_p : std_logic;
	signal tx_n : std_logic;


begin
	trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
		generic map(
			F_CLK     => 49000000,
			F_CLK_PHY => 100000000
		)
		port map(
			clk => clk,
			phy_clk => phy_clk,
			rst => rst,
			phy_out => phy_out,
			phy_in => phy_in,
			rx_p => rx_p,
			tx_p => tx_p,
			tx_n => tx_n
		);

	clock_driver : process
		constant period : time := 20 ns;
	begin
		clk <= '0';
		wait for period / 2;
		clk <= '1';
		wait for period / 2;
	end process clock_driver;

	phy_clock_driver : process
		constant period : time := 10 ns;
	begin
		phy_clk <= '0';
		wait for period / 2;
		phy_clk <= '1';
		wait for period / 2;
	end process phy_clock_driver;

	test : process is
	begin
		rx_p <= '0';

		rst <= '1';
		wait for 20 ns;
		rst <= '0';
		wait for 20 ns;

		send_data(rx_p, byte_vector'(x"55", x"55", x"55", x"D5", x"12", x"34"));
		wait;
	end process test;

	receiver : process is
	begin
		wait until rising_edge(clk);
		if phy_out.rx_data_valid then
			report "RX byte: " & to_hstring(phy_out.rx_data);
		end if;
	end process receiver;

end architecture bench;