90 lines
2.0 KiB
VHDL
90 lines
2.0 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.bench_pkg.all;
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library trashernet;
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use trashernet.trashernet_types.all;
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entity bench_trashernet_phy is
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end entity bench_trashernet_phy;
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architecture bench of bench_trashernet_phy is
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signal clk : std_logic;
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signal phy_clk : std_logic;
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signal rst : std_logic;
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signal rx_data : std_logic_vector(7 downto 0);
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signal rx_data_valid : std_logic;
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signal rx_active : std_logic;
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signal tx_data : std_logic_vector(7 downto 0);
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signal tx_data_en : std_logic;
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signal tx_data_ack : std_logic;
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signal carrier_detect : std_logic;
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signal rx_error : std_logic;
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signal rx_p : std_logic;
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signal tx_p : std_logic;
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begin
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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generic map(
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F_CLK => 49000000,
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F_CLK_PHY => 100000000
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)
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port map(
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clk => clk,
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phy_clk => phy_clk,
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rst => rst,
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rx_data => rx_data,
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rx_data_valid => rx_data_valid,
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rx_active => rx_active,
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tx_data => tx_data,
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tx_data_en => tx_data_en,
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tx_data_ack => tx_data_ack,
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carrier_detect => carrier_detect,
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rx_error => rx_error,
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rx_p => rx_p,
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tx_p => tx_p
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);
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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phy_clock_driver : process
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constant period : time := 10 ns;
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begin
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phy_clk <= '0';
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wait for period / 2;
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phy_clk <= '1';
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wait for period / 2;
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end process phy_clock_driver;
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test : process is
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begin
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rx_p <= '0';
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rst <= '1';
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wait for 20 ns;
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rst <= '0';
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wait for 20 ns;
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send_data(rx_p, byte_vector'(x"55", x"55", x"55", x"D5", x"12", x"34"));
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wait;
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end process test;
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receiver : process is
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begin
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wait until rising_edge(clk);
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if rx_data_valid then
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report "RX byte: " & to_hstring(rx_data);
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end if;
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end process receiver;
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end architecture bench;
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