2022-10-31 16:57:54 +01:00
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- trashernet_eth.vhd : Ethernet OSI Layer 3, Network, Protocol Muxing
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-- Implements arbitration of different IP protocols.
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.trashernet_pkg.all;
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entity trashernet_ipv4prot is
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generic(
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IPV4_PROTOCOLS : ipv4_protocol_vector
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);
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port(
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-- Global
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clk : in std_logic; -- Global clock
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rst : in std_logic; -- Asynchronous reset
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-- IPv4 application interface
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ipv4_out : in ipv4_out_t; -- IPv4 IF (out from IP)
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ipv4_in : out ipv4_in_t; -- IPv4 IF (into IP)
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-- IPv4 protocol interface
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ipv4_protocol_out : out ipv4_protocol_out_vector(IPV4_PROTOCOLS'range); -- IPv4 Protocol IF (out from IP Mux)
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ipv4_protocol_in : in ipv4_protocol_in_vector(IPV4_PROTOCOLS'range) -- IPv4 Protocol IF (into IP Mux)
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);
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end entity trashernet_ipv4prot;
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architecture rtl of trashernet_ipv4prot is
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constant SEL_PROTOCOL_NONE : integer := ipv4_protocol_out'low - 1;
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signal rx_sel : integer range SEL_PROTOCOL_NONE to ipv4_protocol_out'high;
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signal tx_sel : integer range ipv4_protocol_in'low to ipv4_protocol_in'high;
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begin
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rx : block
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signal rx_header_rcv_delayed : std_logic;
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begin
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arb : process(clk, rst) is
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begin
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if rst then
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rx_sel <= SEL_PROTOCOL_NONE;
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rx_header_rcv_delayed <= '0';
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elsif rising_edge(clk) then
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rx_header_rcv_delayed <= ipv4_out.rx_header_rcv;
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if ipv4_out.rx_header_rcv then
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rx_sel <= SEL_PROTOCOL_NONE;
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for i in IPV4_PROTOCOLS'range loop
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if (ipv4_out.rx_protocol = IPV4_PROTOCOLS(i)) then
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rx_sel <= i;
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end if;
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end loop;
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end if;
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end if;
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end process arb;
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mux : for i in ipv4_protocol_out'range generate
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ipv4_protocol_out(i).rx_data <= ipv4_out.rx_data;
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ipv4_protocol_out(i).rx_ip_address <= ipv4_out.rx_ip_address;
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2022-11-01 16:22:59 +01:00
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ipv4_protocol_out(i).rx_length <= ipv4_out.rx_length;
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2022-10-31 16:57:54 +01:00
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ipv4_protocol_out(i).rx_data_valid <= ipv4_out.rx_data_valid when rx_sel = i else '0';
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ipv4_protocol_out(i).rx_error_stb <= ipv4_out.rx_error_stb when rx_sel = i else '0';
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ipv4_protocol_out(i).rx_ok_stb <= ipv4_out.rx_ok_stb when rx_sel = i else '0';
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ipv4_protocol_out(i).rx_header_rcv <= rx_header_rcv_delayed when rx_sel = i else '0';
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end generate mux;
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tx_mux : for i in ipv4_protocol_out'range generate
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ipv4_protocol_out(i).tx_data_ack <= ipv4_out.tx_data_ack when tx_sel = i else '0';
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ipv4_protocol_out(i).tx_err_stb <= ipv4_out.tx_err_stb when tx_sel = i else '0';
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ipv4_protocol_out(i).tx_ok_stb <= ipv4_out.tx_ok_stb when tx_sel = i else '0';
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end generate;
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end block rx;
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tx : block
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type state_t is (IDLE, TXD);
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signal state : state_t;
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begin
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arb : process(clk, rst) is
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begin
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if rst then
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state <= IDLE;
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tx_sel <= ipv4_protocol_in'left;
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elsif rising_edge(clk) then
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case state is
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when IDLE =>
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for i in ipv4_protocol_in'range loop
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if ipv4_protocol_in(i).tx_en then
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tx_sel <= i;
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state <= TXD;
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exit; -- Prioritize according to vector
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end if;
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end loop;
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when TXD =>
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state <= IDLE when (not ipv4_in.tx_en);
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end case;
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end if;
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end process arb;
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demux : block
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begin
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ipv4_in.tx_data <= ipv4_protocol_in(tx_sel).tx_data;
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ipv4_in.tx_en <= ipv4_protocol_in(tx_sel).tx_en;
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ipv4_in.tx_ip_address <= ipv4_protocol_in(tx_sel).tx_ip_address;
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2022-10-31 23:46:46 +01:00
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ipv4_in.tx_length <= ipv4_protocol_in(tx_sel).tx_length;
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2022-10-31 16:57:54 +01:00
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ipv4_in.tx_protocol <= IPV4_PROTOCOLS(tx_sel);
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end block demux;
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end block tx;
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end architecture rtl;
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