78 lines
1.6 KiB
VHDL
78 lines
1.6 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library trashernet;
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entity bench_crc is
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end entity bench_crc;
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architecture bench of bench_crc is
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constant POLYNOMIAL : std_logic_vector(31 downto 0) := x"04C11DB7";
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signal clk : std_logic;
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signal rst : std_logic;
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signal data : std_logic_vector(7 downto 0);
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signal data_valid : std_logic;
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signal crc_clear : std_logic;
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signal crc_out : std_logic_vector(POLYNOMIAL'range);
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begin
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crc_inst : entity trashernet.crc
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generic map(
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POLYNOMIAL => POLYNOMIAL,
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START => x"FFFFFFFF",
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FINAL_XOR => x"FFFFFFFF",
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REVERSE_OUT => true
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)
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port map(
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clk => clk,
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rst => rst,
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data => data,
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data_valid => data_valid,
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crc_clear => crc_clear,
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crc_out => crc_out
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);
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clock_driver : process
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constant period : time := 10 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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test : process is
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procedure send_byte(b : std_logic_vector(data'range)) is
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begin
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data <= b;
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data_valid <= '1';
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wait until rising_edge(clk);
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data_valid <= '0';
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end procedure send_byte;
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variable temp : std_logic_vector(crc_out'range);
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begin
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rst <= '1';
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data_valid <= '0';
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crc_clear <= '0';
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wait for 20 ns;
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rst <= '0';
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wait until rising_edge(clk);
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send_byte(x"01");
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wait until rising_edge(clk);
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report "CRC: " & to_hstring(crc_out);
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for i in 31 downto 0 loop
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temp(i) := crc_out(31 - i);
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end loop;
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report "BITREV: " & to_hstring(temp);
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wait;
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end process test;
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end architecture bench;
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