52 lines
1.0 KiB
VHDL
52 lines
1.0 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity cdc_strobe is
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generic(
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SYNCHRONIZERS : integer := 3
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);
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port(
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a_clk : in std_logic;
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a_rst : in std_logic;
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a_in : in std_logic;
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b_clk : in std_logic;
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b_rst : in std_logic;
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b_out : out std_logic
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);
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end entity cdc_strobe;
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architecture rtl of cdc_strobe is
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signal a_toggle : std_logic;
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signal b_toggle : std_logic;
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signal b_toggle_last : std_logic;
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begin
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togglify : process(a_clk, a_rst) is
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begin
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if a_rst then
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a_toggle <= '0';
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elsif rising_edge(a_clk) then
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if (a_in) then
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a_toggle <= not a_toggle;
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end if;
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end if;
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end process togglify;
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synchronizer_inst : entity work.synchronizer
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generic map(
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SIZE => SYNCHRONIZERS
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)
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port map(
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clk => b_clk,
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rst => b_rst,
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data_in => a_toggle,
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data_out => b_toggle
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);
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-- strobify
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b_toggle_last <= '0' when b_rst
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else b_toggle when rising_edge(b_clk)
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;
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b_out <= (b_toggle ?/= b_toggle_last);
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end architecture rtl;
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