43 lines
1.1 KiB
VHDL
43 lines
1.1 KiB
VHDL
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- pll0.vhd : Simulates the PLL component present in some demo designs
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity pll0 is
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port(
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CLK : in std_logic;
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CLKOP : out std_logic;
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LOCK : out std_logic
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);
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end entity pll0;
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architecture bench of pll0 is
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begin
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clock_driver : process
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constant period : time := 7.1429 ns; -- 140 MHz configured clock
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begin
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CLKOP <= '0';
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LOCK <= '0';
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wait until CLK'event;
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wait for 12 ns;
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LOCK <= '1';
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loop
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CLKOP <= '0';
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wait for period / 2;
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CLKOP <= '1';
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wait for period / 2;
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end loop;
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end process clock_driver;
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end architecture bench;
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